代码搜索：initial
找到约 10,000 项符合「initial」的源代码
代码结果 10,000
www.eeworm.com/read/240355/13221697
txt ds18b20.txt
;*****************************************************
; SAMPLE TEMPRATURE PROGRAM BY DS18B20
; 12.000MHZ OR 11.0592MHZ
;*****************************************************
DQ BIT P3.0
FLAG
www.eeworm.com/read/138383/13238563
cpp determinize.cpp
#include
#include
#include
#include
#include
int main()
{
NFA_mmap nfa;
NFA_mmap::state_type Q[10];
nfa.new
www.eeworm.com/read/324454/13262469
txt dpll_two_tp.txt
module DPLL_two_tp;
reg fout2,reset;
wire fout;
parameter dely=100;
DPLL_two inst_DPLL_two(fout2,idout,reset);
initial
begin fout2=0;reset=0;
#(dely*20) reset=1;
#(dely*20)$stop;
end
www.eeworm.com/read/324454/13262498
bak dpll_xor_tp.v.bak
module DPLL_xor_tp;
reg fin,fout;
wire se;
parameter dely=100;
DPLL_xor inst_DPLL_xor(fin,fout,se);
initial
begin fin=0;fout=0;
#(dely*10) fout=1;
#(dely*10) $stop;
end
always#(dely/2) fin=~fin;
www.eeworm.com/read/324454/13262511
bak dpll_two_tp.v.bak
module DPLL_two_tp;
reg fout2,reset;
wire fout;
parameter dely=100;
DPLL_two inst_DPLL_two(fout2,idout,reset);
initial
begin fout2=0;reset=0;
#(dely*20) reset=1;
#(dely*20)$stop;
end
www.eeworm.com/read/324454/13262523
v dpll_two_tp.v
module DPLL_two_tp;
reg fout2,reset;
wire fout;
parameter dely=100;
DPLL_two inst_DPLL_two(fout2,fout,reset);
initial
begin fout2=0;reset=0;
#(dely*20) reset=1;
#(dely*20)$stop;
end
always #(dely/
www.eeworm.com/read/239424/13281064
inc pcplay.inc
//========================================================================================
// Progarm: The head file for pcplay.asm
// Arranged by: Andy Hsu
// Last modified date:
// 2000/06/23
www.eeworm.com/read/324009/13295473
c uart.c
#include
void UART_initial(void)
{
SCON=0x50;//波特率可变10位通信方式,允许接收.
PCON=0x00;//使用T3时,不再有加倍功能
T3CON = 0x84; //
T3FD = 0x2d; //
IE |= 0x90; //Enable Serial In
www.eeworm.com/read/238934/13314216
v uart_tf.v
`timescale 1ns/1ns
module uart_tf();
wire tbre ;
wire tsre ;
wire sdo ;
reg [7:0] din ;
reg reset ;
reg clk32m ;
reg wrn ;
reg rxd ;
reg rdn ;
wire [7:0] dout ;
wire data_ready ;
wire framing_erro
www.eeworm.com/read/322516/13378132
hif clock_div.hif
Version 7.1 Build 156 04/30/2007 SJ Full Version
11
912
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths