代码搜索：initial
找到约 10,000 项符合「initial」的源代码
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www.eeworm.com/read/260217/11739284
lst timer.lst
C51 COMPILER V7.50 TIMER 12/14/2006 13:34:47 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE TIMER
OBJECT MODULE PLACED IN T
www.eeworm.com/read/157053/11742370
inc a2000.inc
//////////////////////////////////////////////////////////////////////////////////////////
// Progarm: SACM-A2000 API external definition
// Writen by: Andy
// Date: 2000/06/20
///////////////////
www.eeworm.com/read/259465/11788651
c retarget.c
/*
** Copyright (C) ARM Limited, 2001. All rights reserved.
*/
/*
** This implements a 'retarget' layer for low-level IO. Typically, this
** would contain your own target-dependent implement
www.eeworm.com/read/156549/11792980
c retarget.c
/*
* Copyright (C) ARM Limited, 1999. All rights reserved.
*/
/*
This implements a 'retarget' layer for low-level IO. Typically, this would
contain your own target-dependent implementation
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s init.s
;/****************************************Copyright (c)**************************************************
;********************************************************************************************
www.eeworm.com/read/345219/11825780
s initold.s
;引入的外部标号在这声明
IMPORT Main ;C语言主程序入口
IMPORT InitStack ;初始化堆栈
IMPORT TargetResetInit ;目标板基本初始化
;给外部使用的标号在这声明
www.eeworm.com/read/259006/11827397
v boundary_scan_register.v
module Boundary_Scan_Register (data_out, data_in, scan_out, scan_in, shiftDR, mode, clockDR, updateDR);
parameter size = 14;
output [size -1: 0] data_out;
output scan_out;
input [size -1: 0] d
www.eeworm.com/read/259004/11827773
v t_integrator_seq.v
module t_Integrator_Seq ();
parameter word_length = 8;
parameter latency = 4;
wire [word_length -1: 0] data_out;
reg [word_length -1: 0] data_in;
reg hold, LSB_flag, clock, r
www.eeworm.com/read/258648/11848089
plg 抢占式优先数调度算法.plg
Build Log
--------------------Configuration: 抢占式优先数调度算法 - Win32 Debug--------------------
Command Lines
Creating temporary file "C:\DOCUME~1\AD
www.eeworm.com/read/258643/11848341
v nrz_2_manchester_mealy.v
module NRZ_2_Manchester_Mealy (B_out, B_in, clock, reset_b);
output B_out;
input B_in;
input clock, reset_b;
reg [1:0] state, next_state;
reg B_out;
parameter S_0 = 0,
S_1