代码搜索：initial
找到约 10,000 项符合「initial」的源代码
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www.eeworm.com/read/347921/11627853
h digit_tube.h
extern void refresh_digit_tube(void);
extern void digit_tube_initial(void);
extern void digit_tube_test(void);
www.eeworm.com/read/157666/11673992
c cfb_getiv.c
/* LibTomCrypt, modular cryptographic library -- Tom St Denis
*
* LibTomCrypt is a library that provides various cryptographic
* algorithms in a highly modular and flexible manner.
*
* The librar
www.eeworm.com/read/157666/11674162
c cbc_getiv.c
/* LibTomCrypt, modular cryptographic library -- Tom St Denis
*
* LibTomCrypt is a library that provides various cryptographic
* algorithms in a highly modular and flexible manner.
*
* The librar
www.eeworm.com/read/157666/11674352
c ctr_getiv.c
/* LibTomCrypt, modular cryptographic library -- Tom St Denis
*
* LibTomCrypt is a library that provides various cryptographic
* algorithms in a highly modular and flexible manner.
*
* The librar
www.eeworm.com/read/157666/11674606
c ofb_getiv.c
/* LibTomCrypt, modular cryptographic library -- Tom St Denis
*
* LibTomCrypt is a library that provides various cryptographic
* algorithms in a highly modular and flexible manner.
*
* The librar
www.eeworm.com/read/260832/11699882
changelog
---------------------
PatchSet 1
Date: 2004/09/10 19:46:28
Author: ppisa
Branch: HEAD
Tag: (none)
Log:
Initial revision
Members:
COPYING:INITIAL->1.1
Makefile:INITIAL->1.1
README:INITIAL->1.1
www.eeworm.com/read/156456/11802534
bak divf_test.v.bak
`define auto_init
`timescale 1ns/1ns
module divf_divf_test_v_tf();
reg CLK;
reg CLR;
reg [31:0] sysf;
reg [31:0] divf;
wire divf_CLK;
integer i;
integer max;
divf divf_te
www.eeworm.com/read/259007/11827350
v clock_unit.v
module Clock_Unit (clock);
output clock;
reg clock;
parameter delay = 0;
parameter half_cycle = 10;
initial begin
#delay clock = 0;
forever #half_cycle clock = ~clock;
end
endmodule
www.eeworm.com/read/259007/11827356
v clock_prog.v
module Clock_Prog (clock);
output clock;
reg clock;
parameter Latency = 100;
parameter Pulse_Width = 50;
parameter Offset = 50;
initial begin
#0 clock = 0;
#Latency fore
www.eeworm.com/read/259007/11827361
v clock_gen.v
module Clock_Gen (clock);
output clock;
reg clock;
parameter delay = 0;
parameter half_cycle = 5;
initial begin
#delay clock = 0;
forever #half_cycle clock = ~clock;
end
endmodule