clock_unit.v

VerilogHDL_advanced_digital_design_code_Clock_generator VerilogHDL高级数字设计源码Clock_generator

module Clock_Unit (clock);
output clock;
 reg clock;
parameter delay = 0;
parameter half_cycle = 10;
initial begin
#delay clock = 0;
forever #half_cycle clock = ~clock;
end
endmodule