代码搜索：initial
找到约 10,000 项符合「initial」的源代码
代码结果 10,000
www.eeworm.com/read/348078/11613272
c main.c
void PlaySnd(int SndIndex,int DAC_Channel)
{
SACM_A2000_Initial(1);
SACM_A2000_Play(SndIndex,DAC_Channel,3);
while((SACM_A2000_Status()&0x0001)!=0)
{
SACM_A2000_ServiceLoop();
*(unsigned i
www.eeworm.com/read/347921/11627791
h uart.h
extern void rs232_initial(void);
extern void rs232_send_byte(unsigned char);
extern void rs232_send_command(void);
www.eeworm.com/read/156508/11795840
java syspropserver.java
/**
@version 1.10 2001-07-15
@author Cay Horstmann
*/
import org.omg.CosNaming.*;
import org.omg.CORBA.*;
import org.omg.PortableServer.*;
class SysPropImpl extends SysPropPOA
{
www.eeworm.com/read/156508/11795849
java listservices.java
/**
@version 1.00 1999-08-21
@author Cay Horstmann
*/
import org.omg.CORBA.*;
/**
This program lists all initial services supplied by an ORB.
*/
public class ListServices
{
www.eeworm.com/read/259004/11827713
v t_ser_par_conv_32.v
module t_Ser_Par_Conv_32 ();
wire [31:0] Data_out;
wire Shft, write;
reg Data_in;
reg En, clk, rst;
initial #1000 $finish;
initial begin clk = 0; forever #5 clk = ~clk; end
initial begin rs
www.eeworm.com/read/259004/11827721
v t_ser_par_conv_8.v
module t_Ser_Par_Conv_8 ();
wire [7: 0] Data_out;
wire Shft, write;
reg Data_in;
reg En, clk, rst;
initial #1000 $finish;
initial begin clk = 0; forever #5 clk = ~clk; end
initial begin rst
www.eeworm.com/read/259004/11827778
v t_decimator_3.v
module t_decimator_3 ();
parameter word_length = 8;
parameter latency = 4;
wire [(word_length*latency) -1: 0] data_out;
reg [word_length-1:0] data_in;
reg hold;
reg
www.eeworm.com/read/258646/11848196
v gap_finder.v
module Gap_finder(Gap, Data, clk, rst);
output [3: 0] Gap;
input [15: 0] Data;
input clk, rst;
reg [3: 0] k, tmp, Gap; // datapath registers
reg [1: 0] state, next_state;
wire Bit = Dat
www.eeworm.com/read/258643/11848369
v bcd_to_excess_3a.v
module BCD_2_Excess_3 (B_out, B_in, clk, reset);
input B_in, clk, reset;
output B_out;
reg q0, q1, q2;
wire w1, w2, w3, w4, B1, B2;
wire [2:0] state = {q2, q1, q0};
always @ (posedge clk or n
www.eeworm.com/read/155485/11868686
c insepct_votage_main.c
void main()
{system_initial();
while(1)
{
//AD_Convert();
obtain_disp_number();
}
}