代码搜索：initial
找到约 10,000 项符合「initial」的源代码
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www.eeworm.com/read/324473/13261772
v random_tp.v
`timescale 10ns/1ns
module random_tp;
integer data;
integer i;
parameter delay=10;
initial $monitor($time,,,"data=%b",data);
initial
begin
for(i=0; i
www.eeworm.com/read/324473/13261804
v time_dif.v
`timescale 10ns/1ns
module time_dif;
reg ts;
parameter delay=2.6;
initial
begin
#delay ts=1;
#delay ts=0;
#delay ts=1;
#delay ts=0;
end
initial $monitor($time,,,"
www.eeworm.com/read/324473/13261807
v mult_tp.v
`timescale 10ns/1ns
module mult_tp;
reg[7:0] a,b;
wire [15:0] out;
integer i,j;
mult8 m1(out,a,b);
initial
begin
a=0;b=0;
for(i=1;i
www.eeworm.com/read/324454/13262376
txt jk_tp.txt
module JK_tp
reg idclock,reset,j,k;
wire q,qn;
paremeter dely=100;
JK inst_jk(idclock,reset,j,k,q,qn);
initial idclock=0;reset=0;j=0,k=1;
begin
#(dely*20) reset=1;
#(dely*20) j=1;
#(d
www.eeworm.com/read/324454/13262386
bak dpll_tp.v.bak
module DPLL_tp;
reg fin,kclock,reset;
reg[3:0] k;
reg[7:0] N;
reg[7:0] H;
wire fout;
parameter dely=100;
DPLL inst_DPLL(fin,fout,kclock,reset,k,N,H);
initial
begin fin=0;kclock=0;reset=0;k=3;N=64;H
www.eeworm.com/read/324454/13262426
v dpll_tp.v
module DPLL_tp;
reg fin,kclock,reset;
reg[3:0] k;
reg[7:0] N;
reg[7:0] H;
wire fout;
parameter dely=100;
DPLL inst_DPLL(fin,fout,kclock,reset,k,N,H);
initial
begin fin=0;kclock=0;reset=0;k=3;N=64;H
www.eeworm.com/read/324454/13262432
v ffd_tp.v
module FFD_tp;
reg idclock,reset,a;
wire b,c;
parameter dely=100;
FFD inst_FFD(idclock,reset,a,b,c);
initial
begin idclock=0;reset=0;a=0;
#(dely*20) reset=1;
#(dely*20) a=1;
#(dely*20) a=0;
#(dely*2
www.eeworm.com/read/324454/13262464
v dpll_4count_tp.v
module DPLL_4count_tp;
reg idout,reset;
reg[7:0] N;
wire fout2;
parameter dely=100;
DPLL_4count inst_DPLL_4count(fout2,idout,N,reset);
initial
begin idout=1;N=6;reset=0;
#(dely*20) reset=1;
#(dely*
www.eeworm.com/read/324454/13262473
bak dpll_4count_tp.v.bak
module DPLL_4count_tp;
reg idout,reset;
reg[7:0] N;
wire fout2;
parameter dely=100;
DPLL_4count inst_DPLL_4count(fout2,idout,N,reset);
initial
begin idout=1;N=2;reset=0;
#(dely*20) reset=1;
#(dely*
www.eeworm.com/read/324454/13262479
txt ffd_tp.txt
module FFD_tp;
reg idclock,reset,a;
wire b,c;
parameter dely=100;
FFD inst_FFD(idclock,reset,a,b,c);
initial
begin idclock=0;reset=1;a=0;
#(dely*20) reset=0;
#(dely*20) reset=1;
#(dely*20