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找到约 10,000 项符合「fpga」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/149607/12362973

vhd conversion_altera.vhd

-- MAX+plus II VHDL Example -- Conversion Function -- Copyright (c) 1994 Altera Corporation -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee; USE ieee.std_logic_1164.all; USE i
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www.eeworm.com/read/149607/12362990

txt counter_nbit.txt

-- n-Bit Synchronous Counter -- dowload from: www.fpga.com.cn & www.pld.com.cn LIBRARY ieee; USE ieee.Std_logic_1164.ALL; USE ieee.Std_logic_unsigned.ALL; ENTITY cntrnbit IS GENERIC(
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www.eeworm.com/read/227189/14437584

txt 多路选择器（使用when－else语句）.txt

-- Multiplexer 16-to-4 using if-then-elsif-else Statement -- download from www.pld.com.cn & www.fpga.com.cn library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d:
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www.eeworm.com/read/227189/14437614

txt 三态总线（注2）.txt

VHDL:Tri-State Buses download from: http://www.fpga.com.cn prebus.vhd LIBRARY IEEE; USE ieee.std_logic_1164.ALL; ENTITY prebus IS PORT( my_in : IN STD_LOGIC_VECTOR(7 D
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www.eeworm.com/read/125697/14470292

vhd conversion_altera.vhd

-- MAX+plus II VHDL Example -- Conversion Function -- Copyright (c) 1994 Altera Corporation -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee; USE ieee.std_logic_1164.all; USE i
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www.eeworm.com/read/213395/15135683

ant default.ant

// E:\FPGA\CLKGEN // Verilog Annotation Test Bench created by // HDL Bencher 6.1i // Thu Apr 05 11:33:31 2007 `timescale 1ns/1ns module wave; UUT ( ); integer TX_FILE; integer TX
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www.eeworm.com/read/17694/754256

cmd _impact.cmd

setMode -bs setMode -bs setCable -port auto Identify identifyMPM assignFile -p 2 -file "E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/ddr_tx_test.bit" Program -p 2 Identify id
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www.eeworm.com/read/190958/5169933

cdc loopback_cs.cdc

#ChipScope Core Inserter Project File Version 3.0 #Wed Aug 16 16:18:50 MDT 2006 Project.device.designInputFile=C\:\\XUP\\Markets\\PLDs\\Workshops\\courses\\v82_fpga_flow\\xupv2pro\\labsolutions\\ver
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www.eeworm.com/read/190958/5170147

cdc loopback_cs.cdc

#ChipScope Core Inserter Project File Version 3.0 #Wed Aug 16 16:31:26 MDT 2006 Project.device.designInputFile=C\:\\XUP\\Markets\\PLDs\\Workshops\\courses\\v82_fpga_flow\\xupv2pro\\labsolutions\\vhd
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www.eeworm.com/read/325655/3481168

cmd_log comparator.cmd_log

xst -intstyle ise -ifn __projnav/comparator.xst -ofn comparator.syr ngdbuild -intstyle ise -dd f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\comparator\ise\comparator/_ngo -i -p xc
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