loopback_cs.cdc

Xilinx的培训教程的源码 virtex

#ChipScope Core Inserter Project File Version 3.0
#Wed Aug 16 16:31:26 MDT 2006
Project.device.designInputFile=C\:\\XUP\\Markets\\PLDs\\Workshops\\courses\\v82_fpga_flow\\xupv2pro\\labsolutions\\vhdl\\lab6\\coregen_lab\\loopback_cs.ngc
Project.device.designOutputFile=C\:\\XUP\\Markets\\PLDs\\Workshops\\courses\\v82_fpga_flow\\xupv2pro\\labsolutions\\vhdl\\lab6\\coregen_lab\\loopback_cs.ngc
Project.device.deviceFamily=3
Project.device.enableRPMs=true
Project.device.outputDirectory=C\:\\XUP\\Markets\\PLDs\\Workshops\\courses\\v82_fpga_flow\\xupv2pro\\labsolutions\\vhdl\\lab6\\coregen_lab\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=1
Project.filter<0>=
Project.icon.boundaryScanChain=0
Project.icon.disableBUFGInsertion=false
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=clk50MHz
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=out_port<0>
Project.unit<0>.dataChannel<1>=out_port<1>
Project.unit<0>.dataChannel<2>=out_port<2>
Project.unit<0>.dataChannel<3>=out_port<3>
Project.unit<0>.dataChannel<4>=out_port<4>
Project.unit<0>.dataChannel<5>=out_port<5>
Project.unit<0>.dataChannel<6>=out_port<6>
Project.unit<0>.dataChannel<7>=out_port<7>
Project.unit<0>.dataDepth=512
Project.unit<0>.dataEqualsTrigger=false
Project.unit<0>.dataPortWidth=8
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=data_present
Project.unit<0>.triggerChannel<1><0>=read_from_uart
Project.unit<0>.triggerChannel<2><0>=write_to_uart
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCount<1>=1
Project.unit<0>.triggerMatchCount<2>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchCountWidth<1><0>=0
Project.unit<0>.triggerMatchCountWidth<2><0>=0
Project.unit<0>.triggerMatchType<0><0>=0
Project.unit<0>.triggerMatchType<1><0>=0
Project.unit<0>.triggerMatchType<2><0>=0
Project.unit<0>.triggerPortCount=3
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortIsData<1>=true
Project.unit<0>.triggerPortIsData<2>=true
Project.unit<0>.triggerPortWidth<0>=1
Project.unit<0>.triggerPortWidth<1>=1
Project.unit<0>.triggerPortWidth<2>=1
Project.unit<0>.triggerSequencerLevels=2
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro