代码搜索：fpga
找到约 10,000 项符合「fpga」的源代码
代码结果 10,000
www.eeworm.com/read/32721/1035816
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/447870/1694217
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity TOP_FPGA is
port(
top_clk48m : in vl_logic;
top_reset : in vl_logic;
pp1o : out vl_logic_
www.eeworm.com/read/366431/2890775
vhd statmach.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTIT
www.eeworm.com/read/174396/6790005
bak altera2.src.bak
# Altera Max+plus, EMax, Quartus and FPGA license file
FEATURE altera_fpgaexpress alterad 3000.0 permanent uncounted 0 HOSTID=0000e25b7518 ck=0
FEATURE altera_mainwin alterad 3000.0 permanent unco
www.eeworm.com/read/174396/6790009
src altera2.src
# Altera Max+plus, EMax, Quartus and FPGA license file
FEATURE altera_fpgaexpress alterad 3000.0 permanent uncounted 0 HOSTID=02bbccddf0b0 ck=0
FEATURE altera_mainwin alterad 3000.0 permanent unco
www.eeworm.com/read/395324/8185510
txt 最高优先级编码.txt
-- Highest Priority Encoder
-- download from www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity priority is
port(I : in bit_vector(7 downto 0); --input
www.eeworm.com/read/294608/8216984
ucf test_vga.ucf
# XSA Board FPGA pin assignment constraints
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %;
net rst_n loc=E3; # SW2
net clk
www.eeworm.com/read/370579/9595032
txt 最高优先级编码器.txt
-- Highest Priority Encoder
-- download from www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity priority is
port(I : in bit_vector(7 downto 0); --input
www.eeworm.com/read/370579/9595034
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/370579/9595036
vhd 一个简单的状态机.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTIT