test_vga.ucf

an-103005-vgagen.zip是一个VGA显示控制器

# XSA Board FPGA pin assignment constraints

NET      "clk"     TNM_NET =      "clk"; 
TIMESPEC "TS_clk"  =       PERIOD "clk"  10 ns HIGH 50 %; 

net      rst_n     loc=E3; # SW2
net      clk       loc=R8; # 100 MHz clock

# parallel port interface
net ppd<0>    loc=E13; 
net ppd<1>    loc=C16; 
net ppd<2>    loc=E14; 
net ppd<3>    loc=D16; 
net ppd<4>    loc=F13; 
net ppd<5>    loc=E15; 
# net ppd<6> loc=G12;
# net ppd<7> loc=G13;
net pps<3>    loc=L13; 
net pps<4>    loc=C10; 
net pps<5>    loc=D10; 
net pps<6>    loc=J13; 

# VGA signals
net      vsync_n   loc=K1; 
net      hsync_n   loc=K4; 
net      red<0>    loc=J1; 
net      red<1>    loc=M1; 
net      red<2>    loc=T2; 
net      green<0>  loc=H2; 
net      green<1>  loc=K5; 
net      green<2>  loc=R1; 
net      blue<0>   loc=H4; 
net      blue<1>   loc=K3; 
net      blue<2>   loc=L5; 

# SDRAM memory tester pin assignments
net      rst_n     loc=E3; # active-low pushbutton
net      clk       loc=R8; # main clock
net      sclkfb    loc=N8; # feedback SDRAM clock after PCB delays
net      sclk      loc=J4; # clock to SDRAM
net      cke       loc=L1; # SDRAM clock enable
net      cs_n      loc=J3; # SDRAM chip-select
net      ras_n     loc=J2; 
net      cas_n     loc=H3; 
net      we_n      loc=G1; 
net      ba<0>     loc=K2; 
net      ba<1>     loc=L2; 
net      sAddr<0>  loc=L4; 
net      sAddr<1>  loc=N1; 
net      sAddr<2>  loc=N2; 
net      sAddr<3>  loc=M4; 
net      sAddr<4>  loc=T5; 
net      sAddr<5>  loc=N6; 
net      sAddr<6>  loc=M6; 
net      sAddr<7>  loc=T3; 
net      sAddr<8>  loc=N5; 
net      sAddr<9>  loc=P1; 
net      sAddr<10> loc=L3; 
net      sAddr<11> loc=M3; 
net      sAddr<12> loc=M2; 
net      sData<0>  loc=C2; 
net      sData<1>  loc=C1; 
net      sData<2>  loc=F5; 
net      sData<3>  loc=D1; 
net      sData<4>  loc=F3; 
net      sData<5>  loc=F2; 
net      sData<6>  loc=F1; 
net      sData<7>  loc=G3; 
net      sData<8>  loc=G4; 
net      sData<9>  loc=G5; 
net      sData<10> loc=E2; 
net      sData<11> loc=E4; 
net      sData<12> loc=B1; 
net      sData<13> loc=A2; 
net      sData<14> loc=D5; 
net      sData<15> loc=C5; 
net      dqmh      loc=H1; 
net      dqml      loc=G2;