_primary.vhd

这是一个在Fusion系列的AFS600的FPGA

library verilog;
use verilog.vl_types.all;
entity TOP_FPGA is
    port(
        top_clk48m      : in     vl_logic;
        top_reset       : in     vl_logic;
        pp1o            : out    vl_logic_vector(7 downto 0);
        pp2o            : out    vl_logic_vector(2 downto 0);
        p_count         : in     vl_logic
    );
end TOP_FPGA;