代码搜索：fpga
找到约 10,000 项符合「fpga」的源代码
代码结果 10,000
www.eeworm.com/read/125701/14470241
vhd statmach_altera.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTIT
www.eeworm.com/read/125698/14470279
vhd counters_altera.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/125697/14470284
txt adder_nbit_generate.txt
-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); --no.
www.eeworm.com/read/208531/15245741
txt 最高优先级编码器.txt
-- Highest Priority Encoder
-- download from www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity priority is
port(I : in bit_vector(7 downto 0); --input
www.eeworm.com/read/17720/754730
prj decoder.prj
KEY LIBERO "8.3"
KEY CAPTURE "8.3.0.22"
KEY DEFAULT_IMPORT_LOC "E:\Easy FPGA030\BELL\hdl"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "ProASIC3"
KEY VendorTec
www.eeworm.com/read/17889/765589
cdf lcd_283rb06.cdf
/* Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EPCS1) Path("D:/2.83/new edition fpga
www.eeworm.com/read/18154/777187
prj new.prj
KEY LIBERO "8.0"
KEY CAPTURE "8.0.0.40"
KEY DEFAULT_IMPORT_LOC "H:\fpga_test\test\new\stimulus"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "ProASIC3"
KEY Ven
www.eeworm.com/read/32720/887363
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/40396/916580
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/40397/916581
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all