decoder.prj

这是Actel 的FPGA的译码器的VHDL源代码。

KEY LIBERO "8.3"
KEY CAPTURE "8.3.0.22"
KEY DEFAULT_IMPORT_LOC "E:\Easy FPGA030\BELL\hdl"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "ProASIC3"
KEY VendorTechnology_Die ""
KEY VendorTechnology_Package ""
KEY ProjectLocation "E:\programer_new\Decoder\project"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "decoder_top::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST FileManager
VALUE "<project>\component\work\decoder_top\decoder_top.cxf,actgen_cxf"
STATE="utd"
TIME="1216957650"
SIZE="1542"
ENDFILE
VALUE "<project>\component\work\decoder_top\decoder_top.v,hdl"
STATE="utd"
TIME="1216957650"
SIZE="609"
PARENT="<project>\component\work\decoder_top\decoder_top.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\designer\impl1\decoder_top.adb,adb"
STATE="utd"
TIME="1219043332"
SIZE="41472"
ENDFILE
VALUE "<project>\designer\impl1\decoder_top.pdb,pdb"
STATE="utd"
TIME="1219043327"
SIZE="11264"
ENDFILE
VALUE "<project>\designer\impl1\decoder_top_fp\decoder_top.pro,pro"
STATE="utd"
TIME="1219046805"
SIZE="1572"
ENDFILE
VALUE "<project>\designer\impl1\decoder_top_fp_1\decoder_top.pro,pro"
STATE="utd"
TIME="1219046805"
SIZE="1576"
ENDFILE
VALUE "<project>\hdl\KEY.v,hdl"
STATE="utd"
TIME="1219043175"
SIZE="2301"
ENDFILE
VALUE "<project>\smartgen\Decoder\Decoder.cxf,actgen_cxf"
STATE="utd"
TIME="1215671172"
SIZE="1497"
ENDFILE
VALUE "<project>\smartgen\Decoder\Decoder.gen,gen"
STATE="utd"
TIME="1215671172"
SIZE="331"
PARENT="<project>\smartgen\Decoder\Decoder.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\Decoder\Decoder.log,log"
STATE="utd"
TIME="1215671172"
SIZE="1135"
PARENT="<project>\smartgen\Decoder\Decoder.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\Decoder\Decoder.v,hdl"
STATE="utd"
TIME="1215671172"
SIZE="1050"
PARENT="<project>\smartgen\Decoder\Decoder.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\synthesis\Decoder.edn,syn_edn"
STATE="ood"
TIME="1215668328"
SIZE="8167"
ENDFILE
VALUE "<project>\synthesis\Decoder_sdc.sdc,syn_sdc"
STATE="ood"
TIME="1215668328"
SIZE="310"
ENDFILE
VALUE "<project>\synthesis\decoder_top.edn,syn_edn"
STATE="utd"
TIME="1219043188"
SIZE="18338"
ENDFILE
VALUE "<project>\synthesis\decoder_top_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1219043188"
SIZE="379"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "Decoder::work"
FILE "<project>\smartgen\Decoder\Decoder.v,hdl"
LIST ProjectState5.1
LIST Impl1
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\Decoder.edn,syn_edn"
VALUE "<project>\synthesis\Decoder_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\Decoder.v,syn_hdl"
VALUE "<project>\phy_synthesis\Decoder_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\Decoder_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\Decoder_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\Decoder_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\Decoder_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\Decoder.adb,adb"
VALUE "<project>\designer\impl1\Decoder.prb,prb"
VALUE "<project>\designer\impl1\Decoder.stp,stp"
VALUE "<project>\designer\impl1\Decoder_fp\Decoder.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "decoder_top::work"
FILE "<project>\component\work\decoder_top\decoder_top.v,hdl"
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Layout
ideSYNTHESIS(<project>\synthesis\decoder_top.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl1\decoder_top.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\decoder_top.edn,syn_edn"
VALUE "<project>\synthesis\decoder_top_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\decoder_top.v,syn_hdl"
VALUE "<project>\phy_synthesis\decoder_top_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\decoder_top_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\decoder_top_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\decoder_top_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\decoder_top_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\decoder_top.adb,adb"
VALUE "<project>\designer\impl1\decoder_top.prb,prb"
VALUE "<project>\designer\impl1\decoder_top.stp,stp"
VALUE "<project>\designer\impl1\decoder_top_fp\decoder_top.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
Type=CoreConfigurator
Profile=CoreConsole
Tool=CoreConsole v1.3 or later
Location=C:\Core2Console_v1.4\bin\CoreConsole.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Synthesis
Profile=Synplify
Tool=Synplify
Location=D:\Libero\Synplify\synplify_902A2\bin\synplify_pro.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Simulation
Profile=ModelSim
Tool=ModelSim
Location=D:\Libero\Model\win32acoem\modelsim.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Stimulus
Profile=WFL
Tool=WFL
Location=D:\Libero\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
Batch=false
EndProfile
Type=PhySynthesis
Profile=
Tool=
Location=
AdditionalParameter=
Batch=false
EndProfile
Type=Program
Profile=FlashPro
Tool=FlashPro
Location=D:\Libero\FlashPro\bin\FlashPro.exe
AdditionalParameter=
Batch=false
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "Decoder::work"
LIST Impl1
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\Decoder.edn,syn_edn"
VALUE "<project>\synthesis\Decoder_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\Decoder.v,syn_hdl"
VALUE "<project>\phy_synthesis\Decoder_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\Decoder_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\Decoder_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\Decoder_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\Decoder_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\Decoder.adb,adb"
VALUE "<project>\designer\impl1\Decoder.prb,prb"
VALUE "<project>\designer\impl1\Decoder.stp,stp"
VALUE "<project>\designer\impl1\Decoder_fp\Decoder.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "decoder_top::work"
LIST Impl1
LiberoState=Post_Layout
ideSYNTHESIS(<project>\synthesis\decoder_top.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl1\decoder_top.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\decoder_top.edn,syn_edn"
VALUE "<project>\synthesis\decoder_top_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\decoder_top.v,syn_hdl"
VALUE "<project>\phy_synthesis\decoder_top_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\decoder_top_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\decoder_top_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\decoder_top_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\decoder_top_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\decoder_top.adb,adb"
VALUE "<project>\designer\impl1\decoder_top.prb,prb"
VALUE "<project>\designer\impl1\decoder_top.stp,stp"
VALUE "<project>\designer\impl1\decoder_top_fp\decoder_top.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
FILE:<project>\hdl\KEY.v,hdl
SD:decoder_top
ACTIVE_VIEW:0
ENDLIST