new.prj

可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除68013a部分的程序

KEY LIBERO "8.0"
KEY CAPTURE "8.0.0.40"
KEY DEFAULT_IMPORT_LOC "H:\fpga_test\test\new\stimulus"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "ProASIC3"
KEY VendorTechnology_Die "IS4X2M1"
KEY VendorTechnology_Package "pq208"
KEY ProjectLocation "H:\fpga_test\fpga_fifo_0122_02"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "fpga_core::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
VALUE="Impl2",NUM=2
CURREV=2
ENDLIST
LIST FileManager
VALUE "<project>\hdl\fifo_fpga_1280X8.v,hdl"
STATE="utd"
ENDFILE
VALUE "<project>\hdl\fifo_fpga_1280x8.v,hdl"
STATE="utd"
ENDFILE
VALUE "<project>\simulation\run.do,do"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\clk_pll\clk_pll.cxf,actgen_cxf"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\clk_pll\clk_pll.gen,gen"
STATE="utd"
PARENT="<project>\smartgen\clk_pll\clk_pll.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\clk_pll\clk_pll.log,log"
STATE="utd"
PARENT="<project>\smartgen\clk_pll\clk_pll.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\clk_pll\clk_pll.v,hdl"
STATE="utd"
PARENT="<project>\smartgen\clk_pll\clk_pll.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.cxf,actgen_cxf"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.gen,gen"
STATE="utd"
PARENT="<project>\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.log,log"
STATE="utd"
PARENT="<project>\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v,hdl"
STATE="utd"
PARENT="<project>\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\stimulus\ctr_data_tb.v,tb_hdl"
STATE="utd"
ENDFILE
VALUE "<project>\stimulus\fifo_fpga_1280x8_tb.v,tb_hdl"
STATE="utd"
ENDFILE
VALUE "<project>\stimulus\fpga_core_tb.v,tb_hdl"
STATE="utd"
ENDFILE
VALUE "<project>\synthesis\fpga_core.edn,syn_edn"
STATE="utd"
ENDFILE
VALUE "<project>\synthesis\fpga_core_sdc.sdc,syn_sdc"
STATE="utd"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST AssociatedStimulus
LIST fpga_core
VALUE "<project>\stimulus\ctr_data_tb.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
CompilePackage=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=fpga_fpga_1280x8_tb
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=TRUE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
Type=CoreConfigurator
Profile=CoreConsole
Tool=CoreConsole v1.3 or later
Location=C:\CoreConsole_v1.3\bin\CoreConsole.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Synthesis
Profile=Synplify
Tool=Synplify
Location=C:\Libero\Synplify\Synplify_88A1\bin\Synplify.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Simulation
Profile=ModelSim
Tool=ModelSim
Location=C:\Libero\Model\win32acoem\modelsim.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Stimulus
Profile=WFL
Tool=WFL
Location=C:\Libero\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
Batch=false
EndProfile
Type=PhySynthesis
Profile=PALACE
Tool=PALACE
Location=palace_actel.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Program
Profile=FlashPro
Tool=FlashPro
Location=C:\Libero\FlashPro\bin\FlashPro.exe
AdditionalParameter=
Batch=false
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "fpga_core::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSTIMULUSEDITOR=StateSuccess
ideSYNTHESIS(<project>\synthesis\fpga_core.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSTIMULUSEDITOR=StateSuccess
ideSYNTHESIS(<project>\synthesis\fpga_core.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\fpga_core.edn,syn_edn"
VALUE "<project>\synthesis\fpga_core_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\fpga_core.v,syn_hdl"
VALUE "<project>\phy_synthesis\fpga_core_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\fpga_core_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\fpga_core_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\fpga_core_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\fpga_core_palace.v,palace_hdl"
VALUE "<project>\designer\impl2\fpga_core.adb,adb"
VALUE "<project>\designer\impl2\fpga_core.prb,prb"
VALUE "<project>\designer\impl2\fpga_core.pdb,pdb"
VALUE "<project>\designer\impl2\fpga_core.stp,stp"
VALUE "<project>\designer\impl2\fpga_core_fp\fpga_core.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
FILE:<project>\stimulus\fifo_fpga_1280x8_tb.v,tb_hdl
FILE:<project>\stimulus\ctr_data_tb.v,tb_hdl
ACTIVE_VIEW:0
ENDLIST