代码搜索：dataIn

找到约 2,888 项符合「dataIn」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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lst temp.lst

C51 COMPILER V8.08 TEMP 03/18/2009 21:47:28 PAGE 1 C51 COMPILER V8.08, COMPILATION OF MODULE TEMP OBJECT MODULE PLACED IN te
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c temp.c

#define uchar unsigned char #define uint unsigned int #define ulong unsigned long #include #include #include //通过ADC0832采样模拟数据 sbit SCS=P3^6; sbit SCLK=P3^5; sb
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eqn lcok.fit.eqn

-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o
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rpt sample.sim.rpt

Simulator report for sample Sun Jan 07 10:22:20 2007 Version 5.1 Build 176 10/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2
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bak instruc2main.v.bak

// WARNING: Do NOT edit the input and output ports in this file in a text // editor if you plan to continue editing the block that represents it in // the Block Editor! File corruption is VERY likel
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v instruc2main.v

// WARNING: Do NOT edit the input and output ports in this file in a text // editor if you plan to continue editing the block that represents it in // the Block Editor! File corruption is VERY likel
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m symbol_syn.m

clear; load c; Fs=38400; %WCDMA信号的采样率 nsamp=16; %过采样率 delay=3; %根号下升余弦的群时延 datain=c; %这里c为WCDMA系统的扰码数据 Num=length(datain); %计算相关的长度 dataout=RRCsend(datain,Fs,nsamp,delay); %调用子程序
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vhd ad.vhd

--AD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity ad is port(busy:in std_logic; datain:in unsigned(7 downto 0); clk:in std_logic; dataout:out un
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v sdr_data_path.v

module sdr_data_path( CLK, RESET_N, DATAIN, DM, DQOUT, DQM ); `include "Sdram_Params.h" input CLK;
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lst 11.lst

ASEM-51 V1.2 Copyright (c) 1996 by W.W. Heinz PAGE 1 MCS-51 Family Cross Assembler A S E M - 5 1
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