instruc2main.v

来自「FPGA Cycloneii 系列的」· Verilog 代码 · 共 152 行

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II Version 7.1 (Build Build 156 04/30/2007)
// Created on Fri Mar 28 11:41:38 2008

//  Module Declaration
module instruc2main
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	datain1, datain2, datain3, datain4, datain5, recv_over, doppler_step, 
	Gauss_P, Rayleigh_MP, Lognormal, Row_dis_delay, FIFO1_time, FIFO2_time, 
	FIFO3_time, FIFO4_time, FIFO5_time, FIFO6_time, FIFO1_amp, FIFO2_amp, 
	FIFO3_amp, FIFO4_amp, FIFO5_amp, FIFO6_amp
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input [7:0] datain1;
	input [7:0] datain2;
	input [7:0] datain3;
	input [7:0] datain4;
	input [7:0] datain5;
	input recv_over;
	
	output [13:0] doppler_step;
	output [7:0] Gauss_P;
	output [5:0] Rayleigh_MP;
	output [4:0] Lognormal;
	output [11:0] Row_dis_delay;
	output [4:0] FIFO1_time;
	output [4:0] FIFO2_time;
	output [4:0] FIFO3_time;
	output [4:0] FIFO4_time;
	output [4:0] FIFO5_time;
	output [4:0] FIFO6_time;
	output [6:0] FIFO1_amp;
	output [6:0] FIFO2_amp;
	output [6:0] FIFO3_amp;
	output [6:0] FIFO4_amp;
	output [6:0] FIFO5_amp;
	output [6:0] FIFO6_amp;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	reg [13:0] doppler_step;
	reg [7:0] Gauss_P;
	reg [5:0] Rayleigh_MP;
	reg [4:0] Lognormal;
	reg [11:0] Row_dis_delay;
	reg [4:0] FIFO1_time;
	reg [4:0] FIFO2_time;
	reg [4:0] FIFO3_time;
	reg [4:0] FIFO4_time;
	reg [4:0] FIFO5_time;
	reg [4:0] FIFO6_time;
	reg [6:0] FIFO1_amp;
	reg [6:0] FIFO2_amp;
	reg [6:0] FIFO3_amp;
	reg [6:0] FIFO4_amp;
	reg [6:0] FIFO5_amp;
	reg [6:0] FIFO6_amp;
	
	always @(datain1 or datain2 or datain3 or datain4 or datain5)
//	always @(posedge recv_over)
		begin
		case(datain2)
			8'h01://doppler
				begin
					doppler_step[7:0]<=datain5;
					doppler_step[13:8]<=datain4[5:0];
				end
			8'h02://guass
				begin
					Gauss_P<=datain5;
				end
			3://duojing
				begin
					case(datain3)
						1:
							begin
								FIFO1_time<=datain4[4:0];
								FIFO1_amp<=datain5[6:0];
							end
						2:
							begin
								FIFO2_time<=datain4[4:0];
								FIFO2_amp<=datain5[6:0];
							end
						3:
							begin
								FIFO3_time<=datain4[4:0];
								FIFO3_amp<=datain5[6:0];
							end
						4:
							begin
								FIFO4_time<=datain4[4:0];
								FIFO4_amp<=datain5[6:0];
							end
						5:
							begin
								FIFO5_time<=datain4[4:0];
								FIFO5_amp<=datain5[6:0];
							end
						6:
							begin
								FIFO6_time<=datain4[4:0];
								FIFO6_amp<=datain5[6:0];
							end
					endcase
				end
			4://row_dis_delay
				begin
					Row_dis_delay<=datain5*15;
				end
			8'h05://Rayleigh
				begin
					Rayleigh_MP<=datain5[5:0];
				end
			6://Lognormal
				begin
					Lognormal<=datain5[4:0];
				end
			
		endcase
		end
									
					
					
					
					
					
				


endmodule