代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
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www.eeworm.com/read/419416/10869977
twr data_unite.twr
--------------------------------------------------------------------------------
Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
D:/Xilinx/bin/nt/trce.exe -ise
www.eeworm.com/read/418311/10953655
c usb_pic18_v786.c
/*
There is no any garentee for this package. Use on as is basis.
It is provided for learning only. No one can use it for Commercial.
This example show how to use PIC18F4550 as usb device.
Inter
www.eeworm.com/read/270913/11020704
vhd and18.vhd
library ieee;
use ieee.std_logic_1164.all;
entity and18 is
port(
datain: in std_logic_vector(7 downto 0);
dataout: out std_logic_vector(17 downto 0)
);
end and18;
architecture and18 o
www.eeworm.com/read/471274/6900617
m symbol_syn.m
clear;
load c;
Fs=38400; %WCDMA信号的采样率
nsamp=16; %过采样率
delay=3; %根号下升余弦的群时延
datain=c; %这里c为WCDMA系统的扰码数据
Num=length(datain); %计算相关的长度
dataout=RRCsend(datain,Fs,nsamp,delay); %调用子程序
www.eeworm.com/read/468096/6999705
v eth_registers.v
`include "eth_defines.v"
`include "timescale.v"
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
www.eeworm.com/read/468096/6999709
v eth_register.v
`include "timescale.v"
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
in
www.eeworm.com/read/468104/6999835
bak ctrlstsregbi.v.bak
//////////////////////////////////////////////////////////////////////
//// ////
//// ctrlStsRegBI.v
www.eeworm.com/read/468104/6999839
v ctrlstsregbi.v
//////////////////////////////////////////////////////////////////////
//// ////
//// ctrlStsRegBI.v
www.eeworm.com/read/466785/7020728
txt 6.3.5快速排序.txt
DATS EQU 20H
N EQU 5DH
QUEUE EQU 1FH
F DATA 3CH
R DATA 3DH
TST:
MOV DPTR,#LIST
MOV P2,#DATS
MOV R0,#0
MOV R2,#N
CPY:
CLR A
MOVC A,@A+DPTR
MOVX @R0,A
INC DPTR
www.eeworm.com/read/465376/7054024
v eth_registers.v
`include "eth_defines.v"
`include "timescale.v"
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,