and18.vhd

来自「fpga的应用」· VHDL 代码 · 共 14 行

library ieee;
use ieee.std_logic_1164.all;
entity and18 is
	port(
			datain: in std_logic_vector(7 downto 0);
			dataout: out std_logic_vector(17 downto 0)
		);
end and18;
architecture and18 of and18 is
signal data : std_logic_vector(9 downto 0);
begin
data<="0000000000";
dataout<=data&datain;
end and18;