代码搜索：dataIn

找到约 2,888 项符合「dataIn」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/100506/15873019

cpp base64helper.cpp

// ------------------------------------------------------------------------------------ // Copyright 2000 - Microsoft Corporation. // All rights reserved. // // THIS CODE AND INFORMATION IS PROVI
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www.eeworm.com/read/100044/15887526

pas httpasp1.pas

{* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Author: Fran鏾is PIETTE Creation: December 30, 1997 Version: 1.00 Description: Sample program to dem
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www.eeworm.com/read/439403/7710296

v pn_gen_srl_test.v

// 12/22/98 M. Gulotta Modified to remove all (2 clk_8fc cycle) latency from SnapEn. `timescale 1ns / 100ps module pn_gen_test; parameter pn_lngth = 131071; //(2^^17 - 1) reg
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www.eeworm.com/read/243992/12901163

v dp_ram.v

module dp_ram(addr_a,addr_b,datain_a,datain_b,dataout_a,dataout_b,clk,wren_a,wren_b); output [7:0] dataout_a,dataout_b; input [4:0] addr_a,addr_b; input [7:0] datain_a,datain_b; input clk,wren_a,w
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www.eeworm.com/read/214883/15085021

tf pn_gen_srl_test.tf

// 12/22/98 M. Gulotta Modified to remove all (2 clk_8fc cycle) latency from SnapEn. // If a non Virtex device was selected for implementation the following // Compiler directive must be
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www.eeworm.com/read/214883/15085108

v pn_gen_srl_test.v

// 12/22/98 M. Gulotta Modified to remove all (2 clk_8fc cycle) latency from SnapEn. // If a non Virtex device was selected for implementation the following // Compiler directive must be
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www.eeworm.com/read/206514/15293990

tf pn_gen_srl_test.tf

// 12/22/98 M. Gulotta Modified to remove all (2 clk_8fc cycle) latency from SnapEn. // If a non Virtex device was selected for implementation the following // Compiler directive must be
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www.eeworm.com/read/206514/15294025

v pn_gen_srl_test.v

// 12/22/98 M. Gulotta Modified to remove all (2 clk_8fc cycle) latency from SnapEn. // If a non Virtex device was selected for implementation the following // Compiler directive must be
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www.eeworm.com/read/310188/13656570

hier_info clock.hier_info

|reg lock => DataOut0[2]~reg0.CLK lock => DataOut0[1]~reg0.CLK lock => DataOut0[0]~reg0.CLK lock => DataOut1[3]~reg0.CLK lock => DataOut1[2]~reg0.CLK lock => DataOut1[1]~reg0.CLK lock => DataOu
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www.eeworm.com/read/408802/11369505

vhd pn_gen_srl_test.vhd

-- 01/20/01 P. Glover Library IEEE; use IEEE.std_logic_1164.ALL; use std.textio.all; entity pn_gen_test is end pn_gen_test; architecture one of pn_gen_test is COMPONENT iq_pn_gen PORT( clk :
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