dp_ram.v

来自「采用Verilog语言描述的FIFO和双端口RAM源代码。」· Verilog 代码 · 共 28 行

module dp_ram(addr_a,addr_b,datain_a,datain_b,dataout_a,dataout_b,clk,wren_a,wren_b);
output [7:0] dataout_a,dataout_b;
input [4:0] addr_a,addr_b;
input [7:0] datain_a,datain_b;
input clk,wren_a,wren_b;

reg[7:0] dataout_a,dataout_b;
reg[7:0] dataout_a_buffer,dataout_b_buffer;
reg[7:0] mem[0:31];
always@(negedge clk)
	begin
	if(wren_a) mem[addr_a]<=datain_a;
	if(wren_b) mem[addr_b]<=datain_b;
	end
	
	
always@(negedge clk)
	begin
	dataout_a_buffer<=mem[addr_a];
	dataout_b_buffer<=mem[addr_b];
	end
	
always@(posedge clk)
	begin
	dataout_a<=dataout_a_buffer;
	dataout_b<=dataout_b_buffer;
	end
endmodule