代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/161907/10357700
vhd store.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity store is
port( datain : in std_logic_vector(31 downto 0);
clk : in std_logic;
stop : in std_log
www.eeworm.com/read/317239/13506912
vhd calculate.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity calculate is
port(
clk:in std_logic;
lockin: in std_logic;
datain: in
www.eeworm.com/read/317239/13507087
vhd calculate.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity calculate is
port(
clk:in std_logic;
lockin: in std_logic;
datain: in
www.eeworm.com/read/491881/6428054
v encode.v
module encode(
input en,clk,ack,s_empty,
input [15:0] datain,
output reg [17:0] dataout,
output reg s_rdreq);
integer n;
reg parity=0;
//奇偶校验
always @ (posedge clk)
if(e
www.eeworm.com/read/264253/11324251
txt readme.txt
1. compile:
mpicc jacobi.c -o jacobi
2. run:
mpirun -np 4 jacobi
3. result (also in file dataOut.txt):
Input of file "dataIn.txt"
4 5
9.000000 -1.000000 -1.000000 1
www.eeworm.com/read/152508/12108663
v usbf_rx_phy.v
//RX & DPLL
module usbf_rx_phy( clk, rst, fs_ce,
// Transciever Interface
rxd, rxdp, rxdn,
// UTMI Interface
RxValid_o, RxActive_o, RxError_o, DataIn_o,
RxEn_i, LineState)
www.eeworm.com/read/8785/153050
v eth_registers.v
`include "eth_defines.v"
`include "timescale.v"
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
www.eeworm.com/read/10221/183782
v eth_registers.v
`include "eth_defines.v"
`include "timescale.v"
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
www.eeworm.com/read/14792/410692
vhd ad.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out unsigned
www.eeworm.com/read/17540/737640
cpld
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MOORE1 IS
PORT (DATAIN :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
CLK,RST : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO