encode.v

FPGA与dSP的接口

module encode(
   input en,clk,ack,s_empty,
   input [15:0] datain,
   output reg [17:0] dataout,
   output reg s_rdreq);

   integer n;
   reg parity=0;
   //奇偶校验
   always @ (posedge clk)
      if(en==1) 
         begin 
            for(n=0;n<16;n=n+1)
            begin
                parity = datain[n] + parity;
            end
            parity=parity + ack;
            dataout[17]=parity;
         end
      else dataout[17]=0;
   //发送握手信息    
   always @ (posedge clk) 
      if(en==1) dataout[16]=ack;
      else dataout[16]=0;
   //发送对方写请求与本地读请求   
   always @ (posedge clk)
      if(en==1)
         begin
            s_rdreq = (~s_empty) && ack;
            dataout[15] = (~s_empty) && ack;        
         end
      else 
         begin
            s_rdreq = 0;
            dataout[15] = 0;
         end
   //数据
   always @ (posedge clk) 
      if(en==1) dataout[14:0]=datain[14:0]; 
      else dataout[14:0]=0;     
endmodule