decode_tb.v

来自「FPGA与dSP的接口」· Verilog 代码 · 共 24 行

module decode_tb;
   reg en,clk,half_full;
   reg [17:0] datain;
   wire[15:0] dataout;
   wire r_wrreq,data_error;
   wire ack;
   
   decode dut(.en(en),.clk(clk),.half_full(half_full),.datain(datain),.dataout(dataout),.data_error(data_error),.r_wrreq(r_wrreq),.ack(ack));
   
   initial begin
       clk=0;
       forever begin
           #10 clk=~clk;
       end
   end
   initial begin
       en=1;
       half_full=0;
       #15 half_full=1;
       #15 en=0;
       #15 en=1;
   end
   always @ (negedge clk) datain=$random;    
endmodule