代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/278232/10557957
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity data_reg is
port(
data_clk : in vl_logic;
datain : in vl_logic;
reset : in vl_logic;
www.eeworm.com/read/443250/7635367
vhd v7_6.vhd
use std.textio.all;
entity TB is
end TB;
architecture A_TB of TB is
signal CLK : bit;
signal SimEn : bit;
begin
process
file infile : TEXT is in "DataIn.dat";
www.eeworm.com/read/321790/13399130
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
www.eeworm.com/read/347114/11690986
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
www.eeworm.com/read/14022/292162
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
www.eeworm.com/read/17761/756584
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
www.eeworm.com/read/17761/756889
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
www.eeworm.com/read/17761/757270
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
www.eeworm.com/read/17761/757640
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
www.eeworm.com/read/18434/788532
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity io_buf_tri is
port(
datain : in vl_logic;
dataout : out vl_logic;
oe : in vl_logi