v7_6.vhd

来自「台湾全华科技VHDL教材实例」· VHDL 代码 · 共 30 行

use std.textio.all;

entity TB is
end TB;

architecture A_TB of TB is

	signal CLK : bit;
	signal SimEn : bit;
	
begin

	process
        file     infile  	: TEXT is in "DataIn.dat";
        file     outfile 	: TEXT is out "DataOut.dat";
		variable inline   	: LINE;
		variable outline  	: LINE;
		variable DinA    	: integer;     
    begin
    	wait until CLK = '1' and CLK'event;
    		if SimEn = '0' then
				readline(infile,inline);
				read(inline,DinA);
				write(outline,DinA,right,10);
				writeline(outfile,outline);
			end if;
    end process;
    
end A_TB;