_primary.vhd

采用匹配滤波

library verilog;
use verilog.vl_types.all;
entity data_reg is
    port(
        data_clk        : in     vl_logic;
        datain          : in     vl_logic;
        reset           : in     vl_logic;
        dclkm4          : in     vl_logic;
        en_numb         : in     vl_logic_vector(4 downto 0);
        data2encode     : out    vl_logic
    );
end data_reg;