代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/453029/1644880
v dial.v
/*
读入拨码开关8位0 1状态在8位7段数码管相应位上显示0或1。
*/
module dial(clk,rst,datain,dataout,en);
input clk,rst;
input[7:0] datain;
output[7:0] dataout;
reg[7:0] dataout;
output[7:0] en;
reg[7:0] en;
reg[15
www.eeworm.com/read/417821/10975064
java calcworker.java
import java.io.*;
import java.net.*;
public class CalcWorker extends Object {
private InputStream sockIn;
private OutputStream sockOut;
private DataInputStream dataIn;
private DataOutputSt
www.eeworm.com/read/397410/6968162
java calcworker.java
import java.io.*;
import java.net.*;
public class CalcWorker extends Object {
private InputStream sockIn;
private OutputStream sockOut;
private DataInputStream dataIn;
private DataOutputSt
www.eeworm.com/read/468555/6992773
java calcworker.java
import java.io.*;
import java.net.*;
public class CalcWorker extends Object {
private InputStream sockIn;
private OutputStream sockOut;
private DataInputStream dataIn;
private DataOutputSt
www.eeworm.com/read/458941/7285243
java calcworker.java
import java.io.*;
import java.net.*;
public class CalcWorker extends Object {
private InputStream sockIn;
private OutputStream sockOut;
private DataInputStream dataIn;
private DataOutputSt
www.eeworm.com/read/397391/8053331
v fifo64.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module FIFO2(clk, rst, datain, pin, wren, rden, dataout, pout, empty, full);
input clk;
inp
www.eeworm.com/read/16514/676643
v lp_rx_top_stratix.v
module lp_rx_top_stratix (clk,
rst_n,
datain,
inclock,
inclock_en,
rvere,
rcser,
acko,
bcmpi_n,
rdreq,
empty,
rdat
www.eeworm.com/read/16514/676744
v lp_rx_top_cyclone.v
module lp_rx_top_cyclone (clk,
rst_n,
datain,
inclock,
inclock_en,
acko,
bcmpi_n,
rvere,
rcser,
rdreq,
empty,
rdat
www.eeworm.com/read/397063/2404538
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity register8_wlh is
generic(
width : integer := 8
);
port(
datain : in vl_logic_vector;
dataou
www.eeworm.com/read/397063/2404556
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity register8_wl is
generic(
width : integer := 8
);
port(
datain : in vl_logic_vector;
dataout