_primary.vhd

来自「Reed-Solomon 信道编码广泛应用于DVB中」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity register8_wl is
    generic(
        width           : integer := 8
    );
    port(
        datain          : in     vl_logic_vector;
        dataout         : out    vl_logic_vector;
        clock           : in     vl_logic;
        load            : in     vl_logic
    );
end register8_wl;