lp_rx_top_stratix.v

来自「altera fpga 和ts201的linkport接口设计」· Verilog 代码 · 共 62 行

module lp_rx_top_stratix (clk,
			  rst_n,

			  datain,
			  inclock,
			  inclock_en,

			  rvere,
			  rcser,
			  
			  acko,
			  bcmpi_n,
			  
			  rdreq,
			  empty,
			  rdata
			  );

  input clk;
  input rst_n;

  input	[3:0]  datain;
  input        inclock;
  input        inclock_en;

  input        rvere;
  output       rcser;       
  
  output       acko;
  input        bcmpi_n;
  
  input        rdreq;
  output       empty;
  output [32:0] rdata;

  parameter 	DEVICE = "Stratix";

  wire 		empty;
  wire [32:0] 	rdata;

  lp_rx #(DEVICE) lp_rx
    (.clk		(clk),
     .rst_n		(rst_n),
     
     .datain		(datain),
     .inclock		(inclock),
     .inclock_en	(inclock_en),

     .rvere		(rvere),
     .rcser		(rcser),
     
     .acko		(acko),
     .bcmpi_n		(bcmpi_n),
     
     .rdreq		(rdreq),
     .empty		(empty),
     .rdata		(rdata)
     );

endmodule