代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/348886/10861641
hier_info config_dac.hier_info
|config_dac
clk => sdo_in.CLK
clk => waddr[4].CLK
clk => waddr[3].CLK
clk => waddr[2].CLK
clk => waddr[1].CLK
clk => waddr[0].CLK
clk => wdata[7].CLK
clk => wdata[6].CLK
clk => wdata[5].CLK
www.eeworm.com/read/489291/6477831
rpt mycpu.tan.rpt
Timing Analyzer report for mycpu
Wed Nov 21 10:51:50 2007
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
www.eeworm.com/read/345339/11819593
vhd bin27seg.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity bin27seg is
PORT( clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
writ
www.eeworm.com/read/345339/11819599
bak bin27seg.vhd.bak
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity bin27seg is
PORT( clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
writ
www.eeworm.com/read/222378/14693663
dds_hier_info
|dds
clock => subdds:SubDDSi.clock
sclrp => subdds:SubDDSi.sclr
iAMPlifys[0] => subdds:SubDDSi.iamps[0]
iAMPlifys[1] => subdds:SubDDSi.iamps[1]
iAMPlifys[2] => subdds:SubDDSi.iamps[2]
iAMPlifys[
www.eeworm.com/read/236118/14031369
c ohciscsiblk.c
// USB Host Controller OHCI test pattern file
// 09/04/2003 Jeff
#include /* Paradigm C++ standard types */
#include
#include
#include
#include
www.eeworm.com/read/236118/14031375
bak ohciscsiblk.bak
// USB Host Controller OHCI test pattern file
// 09/04/2003 Jeff
#include /* Paradigm C++ standard types */
#include
#include
#include
#include
www.eeworm.com/read/236118/14031431
c ohciscsiblk.c
// USB Host Controller OHCI test pattern file
// 09/04/2003 Jeff
#include /* Paradigm C++ standard types */
#include
#include
#include
#include
www.eeworm.com/read/249356/4452233
v ham_7_4_dec.v
///
module ham_7_4_dec(
clk,
reset,
datain,
dvin,
dvout,
code);
input clk, reset, datain, dvin;
output dvout;
reg dvout;
output code;
reg code;
reg [6:0]
datareg;
reg [6:0]
outdatareg;
reg [
www.eeworm.com/read/293736/3928958
v ham_7_4_dec.v
///
module ham_7_4_dec(
clk,
reset,
datain,
dvin,
dvout,
code);
input clk, reset, datain, dvin;
output dvout;
reg dvout;
output code;
reg code;
reg [6:0]
datareg;
reg [6:0]
outdatareg;
reg [