bin27seg.vhd

vhdl的很多例子

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity bin27seg is
 PORT( clk  :  IN  STD_LOGIC;
       rst  :  IN  STD_LOGIC;
    write_n :  IN  STD_LOGIC;
  writedata :  IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
   seg_data :  OUT STD_LOGIC_VECTOR(7 downto 0);
   seg_com  :  OUT STD_LOGIC_VECTOR(3 downto 0)
 );
END bin27seg;
ARCHITECTURE behav OF bin27seg IS
  
  SIGNAL bcd_led  :  STD_LOGIC_VECTOR(3 DOWNTO 0);
  SIGNAL clkcnt   :  STD_LOGIC_VECTOR(16 DOWNTO 0);
  SIGNAL writedata_r : integer range 0 to 50000000;
  SIGNAL  datain  :  STD_LOGIC_VECTOR(15 DOWNTO 0);
begin


process(write_n,rst,writedata)
  begin
   if (rst='0') then 
     datain <= "0000000000000000";
     elsif (write_n = '0') then
      writedata_r <= conv_integer(writedata)*2500/256;
      datain( 3 downto 0) <= conv_std_logic_vector(writedata_r rem 10,4);
      datain( 7 downto 4) <= conv_std_logic_vector(writedata_r/10 rem 10,4);
      datain(11 downto 8) <= conv_std_logic_vector(writedata_r/100 rem 10,4);
      datain(15 downto 12)<= conv_std_logic_vector(writedata_r/1000 rem 10,4);
   end if;
end process;

process(clk,rst)
begin
  if(rst='0')then
    clkcnt<="00000000000000000";
    elsif(rising_edge(clk))then
     clkcnt<= clkcnt+1;
  end if;
end process;



process(clkcnt(16 downto 15),datain)
 begin
   case clkcnt(16 downto 15) is
      when "00" =>bcd_led<=datain(3  downto 0);seg_com<="1110" ;
      when "01" =>bcd_led<=datain(7  downto 4);seg_com<="1101" ;
      when "10" =>bcd_led<=datain(11 downto 8);seg_com<="1011" ;
      when "11" =>bcd_led<=datain(15 downto 12);seg_com<="0111" ;
      when others => NULL;
   end case;
end process;

process(bcd_led)
	begin
			case bcd_led is
				when "0000" => seg_data <= "11000000"; -- 0
				when "0001" => seg_data <= "11111001"; -- 1
				when "0010" => seg_data <= "10100100"; -- 2
				when "0011" => seg_data <= "10110000"; -- 3
				when "0100" => seg_data <= "10011001"; -- 4
				when "0101" => seg_data <= "10010010"; -- 5
				when "0110" => seg_data <= "10000010"; -- 6
				when "0111" => seg_data <= "11111000"; -- 7
				when "1000" => seg_data <= "10000000"; -- 8
				when "1001" => seg_data <= "10010000"; -- 9
				when "1010" => seg_data <= "10001000"; -- A
				when "1011" => seg_data <= "10000011"; -- b
				when "1100" => seg_data <= "10100111"; -- c
				when "1101" => seg_data <= "10100001"; -- d
				when "1110" => seg_data <= "10000110"; -- E
				when "1111" => seg_data <= "10001110"; -- F
				when others => NULL;
			end case;
	end process;
	
--dataout<=bcd_led;

end behav;

------------------------------------------------------------------------------------
-- DESCRIPTION   :   BIN to seven segments converter
--                   segment encoding
--                        a
--                      +---+ 
--                    f |   | b
--                      +---+  <- g
--                    e |   | c
--                      +---+
--                        d
--                  Outputs (data_out) active         : low
------------------------------------------------------------------------------------