代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/475934/6770109
vhd xianshi.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY XIANSHI IS
PORT (
RST : IN STD_LOGIC;
c
www.eeworm.com/read/393841/8260034
vqm sdr_sdram.vqm
//
// Written by Synplify
// Tue Jun 06 11:39:16 2000
//
// Source file index table:
// Object locations will have the form :
// file 0 "noname"
// file 1 "\d:\program files\synplic
www.eeworm.com/read/393841/8260229
vqm sdr_sdram.vqm
//
// Written by Synplify
// Tue Jun 06 11:39:16 2000
//
// Source file index table:
// Object locations will have the form :
// file 0 "noname"
// file 1 "\d:\program files\synplic
www.eeworm.com/read/415978/11046280
vqm sdr_sdram.vqm
//
// Written by Synplify
// Wed Jul 12 11:11:13 2000
//
// Source file index table:
// Object locations will have the form :
// file 0 "noname"
// file 1 "\d:\projects\altera\lpcor
www.eeworm.com/read/413451/11155316
vwf pro4.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/335372/12532097
searchresults communication.searchresults
---- PSD_REG_BASE Matches (2 in 2 files) ----
Upsd3200.h: unsigned char DATAIN_A; // PSD_REG_BASE +0x00
Upsd_flash.h:#define PSD_REG_BASE (unsigned int) 0x0200 // base address of PSD8
www.eeworm.com/read/203724/15352629
muxcntlr_hier_info
|muxcntlr
CLE_EM_A2 => i19.DATAB
CLE_EM_A2 => i44.DATAB
ALE_EM_A1 => i17.DATAB
ALE_EM_A1 => i42.DATAB
ATA2_EM_A0 => i38.DATAB
ATA2_EM_A0 => i40.DATAB
ATA1_EM_BA1 => i36.DATAB
ATA0_EM_BA0 => i3
www.eeworm.com/read/102365/15784953
csf ddr_sdram.csf
REPORT_TAN_TSU_SETTINGS("||Compilation Report||Results for \"ddr_sdram\" Compiler Settings||Timing Analyses||tco (Clock to Output Delays)")
{
REPORT_OUTPUT_SECTION = ON;
PAGE_ORIENTATION = PORTRA
www.eeworm.com/read/159159/10687903
v rxunit.v
module RxUNIT(Clk, Reset, Enable, RxD, RD, FErr, OErr, DRdy, DataIn);
input Clk;
input Reset;
input Enable;
input RxD;
input RD;
output FErr;
output OErr;
output DRdy;
output[7:0] DataIn;
www.eeworm.com/read/130423/14194843
bak convencdja.bak
`timescale 1ns/10ps
// TOP_ENCODE
//--------------------
module top_encode(clk, rst, dataIn, serialData, parData);
input clk, rst, dataIn;
output serialData;
output [1:0] parData;
wire se