rxunit.v

UART verilog hdl 实现

module RxUNIT(Clk, Reset, Enable, RxD, RD, FErr, OErr, DRdy, DataIn);

input Clk;
input Reset;
input Enable;
input RxD;
input RD;
output FErr;
output OErr;
output DRdy;
output[7:0] DataIn;

//内部信号定义
reg Start;
reg tmpRxD;
reg tmpDRdy;
reg outErr;
reg frameErr;
reg[3:0] tmpBitCnt;
reg[3:0] tmpSampleCnt;
reg[3:0] BitCnt;
reg[3:0] SampleCnt;
reg[7:0] ShtReg;
reg[7:0] DOut; 
//

always@(posedge Clk)
begin
	tmpBitCnt[3:0] = BitCnt[3:0];
	tmpSampleCnt[3:0] = SampleCnt[3:0];
	if(Reset==0)begin
		BitCnt = 4'b0000;
		SampleCnt = 4'b0000;
		Start = 0;
		tmpDRdy = 0;
		frameErr = 0;
		outErr = 0;
		ShtReg[7:0] = 8'b00000000;
		DOut[7:0] = 8'b00000000; 
	end else begin
		if(RD==1)begin
			tmpDRdy = 0;
		end else if(tmpBitCnt==4'b1001)begin
			tmpDRdy = 1;
		end
	
		if(Enable==1)begin
			if(Start==0)begin
				if(RxD==0)begin
					SampleCnt = SampleCnt + 1;
					Start = 1;
				end
			end else begin
				if(tmpSampleCnt==4'b1000)begin
					tmpRxD = RxD;
					SampleCnt = SampleCnt + 1;
				end else if(tmpSampleCnt==4'b1111)begin
					case(tmpBitCnt)
					4'b0000:begin
							if(tmpRxD==1)begin
								Start = 0;
							end else begin
								BitCnt = BitCnt + 1;
							end
							SampleCnt = SampleCnt + 1;
							end
					4'b0001,
					4'b0010,
					4'b0011,
					4'b0100,
					4'b0101,
					4'b0110,
					4'b0111,
					4'b1000:begin
							BitCnt = BitCnt + 1;
							SampleCnt = SampleCnt + 1;
							ShtReg[7:0] = {tmpRxD, ShtReg[7:1]};
							end
					4'b1001:begin
							if(tmpRxD==0)begin
								frameErr = 1;
							end else begin
								frameErr = 0;
							end
						
							if(tmpDRdy==1)begin
								outErr = 1;
							end else begin
								outErr = 0;
							end
							
							DOut = ShtReg;
							BitCnt[3:0] = 4'b0000;
							Start = 0; 
							end
					default: ;
					endcase
				end else begin
					SampleCnt = SampleCnt + 1;
				end
			end
		end
	end
end

assign DRdy = tmpDRdy;
assign DataIn = DOut;
assign FErr = frameErr;
assign OErr = outErr;
 
endmodule