代码搜索：dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/392298/8351995

hier_info jiaozhijiejiaozhi.hier_info

|jiaozhijiejiaozhi output interlace:inst.clk clk => jieinterlace:inst1.clk output3
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www.eeworm.com/read/392298/8352004

hier_info jieinterlace.hier_info

|jiaozhijiejiaozhi output jieinterlace:inst2.clk clk => interlace:inst.clk output3
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www.eeworm.com/read/392298/8352165

hier_info interlace.hier_info

|interlace d1 RAM_MN_dual:inst5.CLK clk => counter:inst8.clk clk => source:inst1.clk clk => rom_mn_interlace:inst.clk clk => rom_mn_seq:inst9.clk clk => RAM_MN_
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www.eeworm.com/read/370803/9584965

m rs_enc.m

function data_out = rs_enc(data_in,m,n,k,genpoly) reg_out =gf(zeros(1,n-k+1),m); % mult_out =gf(zeros(1,n-k),m); % regout =zeros(1,n-k); % adderout =zeros(1,n-k); % multout =zeros(1,n-k); % data
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www.eeworm.com/read/103567/15728946

xrf ddr_sdram.xrf

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, d:\program files\synplicity_60\synplify\lib\vhd\std.vhd, synplify source_file = 2, d:\projects\altera\lpcores\ddr\release
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www.eeworm.com/read/102365/15784999

xrf ddr_sdram.xrf

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_sdram.v, synplify source_file = 2, d:\projects\alter
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www.eeworm.com/read/102365/15785006

xrf ddr_data_path.xrf

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_sdram.v, synplify source_file = 2, d:\projects\alter
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www.eeworm.com/read/453687/7414480

v sample.v

module sample(clk,enable,reset,dataIn,EOC,ALE,START,OE,ADDA,dataOut,dataINT); input clk; input enable; input reset; input [7:0] dataIn; input EOC; output reg ALE;
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www.eeworm.com/read/309317/13674251

v sample.v

module sample(clk,enable,reset,dataIn,EOC,ALE,START,OE,ADDA,dataOut,dataINT); input clk; input enable; input reset; input [7:0] dataIn; input EOC; output reg ALE;
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www.eeworm.com/read/17670/753444

drc lvds_tx_rx_merge.drc

WARNING:PhysDesignRules:1412 - Dangling pins on block::. When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignor
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