sample.v

运行在FPGA上的Verilog程序

module sample(clk,enable,reset,dataIn,EOC,ALE,START,OE,ADDA,dataOut,dataINT);
    input clk;
    input enable;
    input reset;
    input [7:0] dataIn;
    input EOC;

    output reg ALE;
    output reg START;
    output reg OE;
    output reg ADDA;
    output reg [7:0] dataOut;
    output reg dataINT;

    reg [2:0] current_state, next_state;    

    parameter state0=3'b000,
              state1=3'b001,
              state2=3'b010,
              state3=3'b011,
              state4=3'b100;

    always @ (posedge clk or posedge reset)
    begin
        if(reset) current_state=state0;
        else if(enable) current_state<=next_state;
        else current_state<=current_state;
    end

    always @ (current_state, EOC)
    begin
        case (current_state)
            state0:begin
                   ALE<=1'b0;
                   START<=1'b0;
                   OE<=1'b0;
                   dataINT<=1'b0;
                   ADDA<=1'b1;// use IN1
                   next_state<=state1;
                   end
            state1:begin
                   ALE<=1'b1;
                   START<=1'b1;
                   OE<=1'b0;
                   dataINT<=1'b0;
                   next_state<=state2;
                   end
            state2:begin
                   ALE<=1'b0;
                   START<=1'b0;
                   OE<=1'b0;
                   dataINT<=1'b0;
                   if(EOC) next_state<=state3;
                   else next_state<=state2;
                   end
            state3:begin
                   ALE<=1'b0;
                   START<=1'b0;
                   OE<=1'b1;
                   dataINT<=1'b0;
                   next_state<=state4;
                   end
            state4:begin
                   ALE<=1'b0;
                   START<=1'b0;
                   OE<=1'b1;
                   dataOut<=dataIn;
                   dataINT<=1'b1;// trigger
                   next_state<=state0;
                   end
            default: next_state<=state0;
        endcase
    end

endmodule