代码搜索:dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
www.eeworm.com/read/359197/10161800

xrf ddr_data_path.xrf

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_sdram.v, synplify source_file = 2, d:\projects\alter
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logdb firfilter.cmp.logdb

v1 DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,mult:mult_7|lpm_mult:lpm_mult_component|mult_r7q:auto_generated|mac_out1, DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,mult:mult_6|lpm_mult:lpm_mult_component|m
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vwf boxing.vwf

/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to
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vhd data_depart.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for ins
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irda_hier_info

|irda clk => pulse_cnt[2].CLK clk => pulse_cnt[1].CLK clk => pulse_cnt[0].CLK clk => slow_cnt[23].CLK clk => slow_cnt[22].CLK clk => slow_cnt[21].CLK clk => slow_cnt[20].CLK clk => slow_cnt[19
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hier_info hamming.hier_info

|hamming choice => s[4]$latch.LATCH_ENABLE choice => s[3]$latch.LATCH_ENABLE choice => s[2]$latch.LATCH_ENABLE choice => s[1]$latch.LATCH_ENABLE choice => s[0]$latch.LATCH_ENABLE choice => data_
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c twi_primitives.c

/***************************************************************************** * TWI_primitives.c * * Copyright (c) 2007 Analog Devices, Inc. All Rights Reserved. * This software is propriet
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eqn part1.map.eqn

-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o
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vwf part1.vwf

/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to
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hier_info ad.hier_info

|ad clk => clk1k:u1.clkin reset => ad0804:u2.reset ad_int => ad0804:u2.ad_int data_i[0] => ad0804:u2.data_i[0] data_i[1] => ad0804:u2.data_i[1] data_i[2] => ad0804:u2.data_i[2] data_i[3] => ad0