ad.hier_info

FPGA控制串行AD（AD0804）,状态机实现

|ad
clk => clk1k:u1.clkin
reset => ad0804:u2.reset
ad_int => ad0804:u2.ad_int
data_i[0] => ad0804:u2.data_i[0]
data_i[1] => ad0804:u2.data_i[1]
data_i[2] => ad0804:u2.data_i[2]
data_i[3] => ad0804:u2.data_i[3]
data_i[4] => ad0804:u2.data_i[4]
data_i[5] => ad0804:u2.data_i[5]
data_i[6] => ad0804:u2.data_i[6]
data_i[7] => ad0804:u2.data_i[7]
cs <= ad0804:u2.cs
wr <= ad0804:u2.wr
rd <= ad0804:u2.rd
en[3] <= display:u4.en[3]
en[2] <= display:u4.en[2]
en[1] <= display:u4.en[1]
en[0] <= display:u4.en[0]
displayA[6] <= display:u4.display[6]
displayA[5] <= display:u4.display[5]
displayA[4] <= display:u4.display[4]
displayA[3] <= display:u4.display[3]
displayA[2] <= display:u4.display[2]
displayA[1] <= display:u4.display[1]
displayA[0] <= display:u4.display[0]


|ad|clk1k:u1
clkin => clk2.CLK
clkin => counter2[0].CLK
clkin => counter2[1].CLK
clkin => counter2[2].CLK
clkin => counter2[3].CLK
clkin => counter2[4].CLK
clkin => clk1.CLK
clkin => counter1[0].CLK
clkin => counter1[1].CLK
clkin => counter1[2].CLK
clkin => counter1[3].CLK
clkin => counter1[4].CLK
clkin => counter1[5].CLK
clkin => counter1[6].CLK
clkin => counter1[7].CLK
clkin => counter1[8].CLK
clkin => counter1[9].CLK
clkin => counter1[10].CLK
clkin => counter1[11].CLK
clkin => counter1[12].CLK
clkin => counter1[13].CLK
newclk1 <= clk1.DB_MAX_OUTPUT_PORT_TYPE
newclk2 <= clk2.DB_MAX_OUTPUT_PORT_TYPE


|ad|ad0804:u2
reset => data_r[0].ACLR
reset => data_r[1].ACLR
reset => data_r[2].ACLR
reset => data_r[3].ACLR
reset => data_r[4].ACLR
reset => data_r[5].ACLR
reset => data_r[6].ACLR
reset => data_r[7].ACLR
reset => current_state~1.IN1
clk => data_r[0].CLK
clk => data_r[1].CLK
clk => data_r[2].CLK
clk => data_r[3].CLK
clk => data_r[4].CLK
clk => data_r[5].CLK
clk => data_r[6].CLK
clk => data_r[7].CLK
clk => current_state~0.IN1
ad_int => Selector0.IN3
ad_int => next_state.read1.DATAB
data_i[0] => data_r[0].DATAIN
data_i[1] => data_r[1].DATAIN
data_i[2] => data_r[2].DATAIN
data_i[3] => data_r[3].DATAIN
data_i[4] => data_r[4].DATAIN
data_i[5] => data_r[5].DATAIN
data_i[6] => data_r[6].DATAIN
data_i[7] => data_r[7].DATAIN
data_o[0] <= data_r[0].DB_MAX_OUTPUT_PORT_TYPE
data_o[1] <= data_r[1].DB_MAX_OUTPUT_PORT_TYPE
data_o[2] <= data_r[2].DB_MAX_OUTPUT_PORT_TYPE
data_o[3] <= data_r[3].DB_MAX_OUTPUT_PORT_TYPE
data_o[4] <= data_r[4].DB_MAX_OUTPUT_PORT_TYPE
data_o[5] <= data_r[5].DB_MAX_OUTPUT_PORT_TYPE
data_o[6] <= data_r[6].DB_MAX_OUTPUT_PORT_TYPE
data_o[7] <= data_r[7].DB_MAX_OUTPUT_PORT_TYPE
cs <= cs~0.DB_MAX_OUTPUT_PORT_TYPE
wr <= current_state.start.DB_MAX_OUTPUT_PORT_TYPE
rd <= current_state.read1.DB_MAX_OUTPUT_PORT_TYPE


|ad|fenwei:u3
numin[0] => numA[0].DATAIN
numin[1] => numA[1].DATAIN
numin[2] => numA[2].DATAIN
numin[3] => numA[3].DATAIN
numin[4] => numB[0].DATAIN
numin[5] => numB[1].DATAIN
numin[6] => numB[2].DATAIN
numin[7] => numB[3].DATAIN
numA[0] <= numin[0].DB_MAX_OUTPUT_PORT_TYPE
numA[1] <= numin[1].DB_MAX_OUTPUT_PORT_TYPE
numA[2] <= numin[2].DB_MAX_OUTPUT_PORT_TYPE
numA[3] <= numin[3].DB_MAX_OUTPUT_PORT_TYPE
numB[0] <= numin[4].DB_MAX_OUTPUT_PORT_TYPE
numB[1] <= numin[5].DB_MAX_OUTPUT_PORT_TYPE
numB[2] <= numin[6].DB_MAX_OUTPUT_PORT_TYPE
numB[3] <= numin[7].DB_MAX_OUTPUT_PORT_TYPE


|ad|display:u4
clock => display[6]~reg0.CLK
clock => display[5]~reg0.CLK
clock => display[4]~reg0.CLK
clock => display[3]~reg0.CLK
clock => display[2]~reg0.CLK
clock => display[1]~reg0.CLK
clock => display[0]~reg0.CLK
clock => en[3]~reg0.CLK
clock => en[2]~reg0.CLK
clock => en[1]~reg0.CLK
clock => en[0]~reg0.CLK
clock => counter[0].CLK
clock => counter[1].CLK
numA[0] => Mux7.IN0
numA[1] => Mux6.IN0
numA[2] => Mux5.IN0
numA[3] => Mux4.IN0
numB[0] => Mux7.IN1
numB[1] => Mux6.IN1
numB[2] => Mux5.IN1
numB[3] => Mux4.IN1
numC[0] => Mux7.IN2
numC[1] => Mux6.IN2
numC[2] => Mux5.IN2
numC[3] => Mux4.IN2
numD[0] => Mux7.IN3
numD[1] => Mux6.IN3
numD[2] => Mux5.IN3
numD[3] => Mux4.IN3
en[3] <= en[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
en[2] <= en[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
en[1] <= en[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
en[0] <= en[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[6] <= display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[5] <= display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[4] <= display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[3] <= display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[2] <= display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[1] <= display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[0] <= display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE