part1.map.eqn

基于FPGA的CPU设计 VHDL 编写

-- Copyright (C) 1991-2005 Altera Corporation
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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--D1_q_a[0] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[0]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[0]_PORT_A_data_in = DATAIN[0];
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_B_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[0]_PORT_B_address_reg = DFFE(D1_q_a[0]_PORT_B_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = WR;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = CLOCK;
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, D1_q_a[0]_PORT_B_address_reg, D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[0] = D1_q_a[0]_PORT_A_data_out[0];


--D1_q_a[1] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[1]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[1]_PORT_A_data_in = DATAIN[1];
D1_q_a[1]_PORT_A_data_in_reg = DFFE(D1_q_a[1]_PORT_A_data_in, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[1]_PORT_A_address_reg = DFFE(D1_q_a[1]_PORT_A_address, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_B_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[1]_PORT_B_address_reg = DFFE(D1_q_a[1]_PORT_B_address, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_PORT_A_write_enable = WR;
D1_q_a[1]_PORT_A_write_enable_reg = DFFE(D1_q_a[1]_PORT_A_write_enable, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_clock_0 = CLOCK;
D1_q_a[1]_PORT_A_data_out = MEMORY(D1_q_a[1]_PORT_A_data_in_reg, , D1_q_a[1]_PORT_A_address_reg, D1_q_a[1]_PORT_B_address_reg, D1_q_a[1]_PORT_A_write_enable_reg, , , , D1_q_a[1]_clock_0, , , , , );
D1_q_a[1] = D1_q_a[1]_PORT_A_data_out[0];


--D1_q_a[2] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[2]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[2]_PORT_A_data_in = DATAIN[2];
D1_q_a[2]_PORT_A_data_in_reg = DFFE(D1_q_a[2]_PORT_A_data_in, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[2]_PORT_A_address_reg = DFFE(D1_q_a[2]_PORT_A_address, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_B_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[2]_PORT_B_address_reg = DFFE(D1_q_a[2]_PORT_B_address, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_PORT_A_write_enable = WR;
D1_q_a[2]_PORT_A_write_enable_reg = DFFE(D1_q_a[2]_PORT_A_write_enable, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_clock_0 = CLOCK;
D1_q_a[2]_PORT_A_data_out = MEMORY(D1_q_a[2]_PORT_A_data_in_reg, , D1_q_a[2]_PORT_A_address_reg, D1_q_a[2]_PORT_B_address_reg, D1_q_a[2]_PORT_A_write_enable_reg, , , , D1_q_a[2]_clock_0, , , , , );
D1_q_a[2] = D1_q_a[2]_PORT_A_data_out[0];


--D1_q_a[3] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[3]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[3]_PORT_A_data_in = DATAIN[3];
D1_q_a[3]_PORT_A_data_in_reg = DFFE(D1_q_a[3]_PORT_A_data_in, D1_q_a[3]_clock_0, , , );
D1_q_a[3]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[3]_PORT_A_address_reg = DFFE(D1_q_a[3]_PORT_A_address, D1_q_a[3]_clock_0, , , );
D1_q_a[3]_PORT_B_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[3]_PORT_B_address_reg = DFFE(D1_q_a[3]_PORT_B_address, D1_q_a[3]_clock_0, , , );
D1_q_a[3]_PORT_A_write_enable = WR;
D1_q_a[3]_PORT_A_write_enable_reg = DFFE(D1_q_a[3]_PORT_A_write_enable, D1_q_a[3]_clock_0, , , );
D1_q_a[3]_clock_0 = CLOCK;
D1_q_a[3]_PORT_A_data_out = MEMORY(D1_q_a[3]_PORT_A_data_in_reg, , D1_q_a[3]_PORT_A_address_reg, D1_q_a[3]_PORT_B_address_reg, D1_q_a[3]_PORT_A_write_enable_reg, , , , D1_q_a[3]_clock_0, , , , , );
D1_q_a[3] = D1_q_a[3]_PORT_A_data_out[0];


--D1_q_a[4] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[4]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[4]_PORT_A_data_in = DATAIN[4];
D1_q_a[4]_PORT_A_data_in_reg = DFFE(D1_q_a[4]_PORT_A_data_in, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[4]_PORT_A_address_reg = DFFE(D1_q_a[4]_PORT_A_address, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_PORT_B_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[4]_PORT_B_address_reg = DFFE(D1_q_a[4]_PORT_B_address, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_PORT_A_write_enable = WR;
D1_q_a[4]_PORT_A_write_enable_reg = DFFE(D1_q_a[4]_PORT_A_write_enable, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_clock_0 = CLOCK;
D1_q_a[4]_PORT_A_data_out = MEMORY(D1_q_a[4]_PORT_A_data_in_reg, , D1_q_a[4]_PORT_A_address_reg, D1_q_a[4]_PORT_B_address_reg, D1_q_a[4]_PORT_A_write_enable_reg, , , , D1_q_a[4]_clock_0, , , , , );
D1_q_a[4] = D1_q_a[4]_PORT_A_data_out[0];


--D1_q_a[5] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[5]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[5]_PORT_A_data_in = DATAIN[5];
D1_q_a[5]_PORT_A_data_in_reg = DFFE(D1_q_a[5]_PORT_A_data_in, D1_q_a[5]_clock_0, , , );
D1_q_a[5]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[5]_PORT_A_address_reg = DFFE(D1_q_a[5]_PORT_A_address, D1_q_a[5]_clock_0, , , );
D1_q_a[5]_PORT_B_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[5]_PORT_B_address_reg = DFFE(D1_q_a[5]_PORT_B_address, D1_q_a[5]_clock_0, , , );
D1_q_a[5]_PORT_A_write_enable = WR;
D1_q_a[5]_PORT_A_write_enable_reg = DFFE(D1_q_a[5]_PORT_A_write_enable, D1_q_a[5]_clock_0, , , );
D1_q_a[5]_clock_0 = CLOCK;
D1_q_a[5]_PORT_A_data_out = MEMORY(D1_q_a[5]_PORT_A_data_in_reg, , D1_q_a[5]_PORT_A_address_reg, D1_q_a[5]_PORT_B_address_reg, D1_q_a[5]_PORT_A_write_enable_reg, , , , D1_q_a[5]_clock_0, , , , , );
D1_q_a[5] = D1_q_a[5]_PORT_A_data_out[0];


--D1_q_a[6] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[6]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[6]_PORT_A_data_in = DATAIN[6];
D1_q_a[6]_PORT_A_data_in_reg = DFFE(D1_q_a[6]_PORT_A_data_in, D1_q_a[6]_clock_0, , , );
D1_q_a[6]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[6]_PORT_A_address_reg = DFFE(D1_q_a[6]_PORT_A_address, D1_q_a[6]_clock_0, , , );
D1_q_a[6]_PORT_B_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[6]_PORT_B_address_reg = DFFE(D1_q_a[6]_PORT_B_address, D1_q_a[6]_clock_0, , , );
D1_q_a[6]_PORT_A_write_enable = WR;
D1_q_a[6]_PORT_A_write_enable_reg = DFFE(D1_q_a[6]_PORT_A_write_enable, D1_q_a[6]_clock_0, , , );
D1_q_a[6]_clock_0 = CLOCK;
D1_q_a[6]_PORT_A_data_out = MEMORY(D1_q_a[6]_PORT_A_data_in_reg, , D1_q_a[6]_PORT_A_address_reg, D1_q_a[6]_PORT_B_address_reg, D1_q_a[6]_PORT_A_write_enable_reg, , , , D1_q_a[6]_clock_0, , , , , );
D1_q_a[6] = D1_q_a[6]_PORT_A_data_out[0];


--D1_q_a[7] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[7]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[7]_PORT_A_data_in = DATAIN[7];
D1_q_a[7]_PORT_A_data_in_reg = DFFE(D1_q_a[7]_PORT_A_data_in, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[7]_PORT_A_address_reg = DFFE(D1_q_a[7]_PORT_A_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_PORT_B_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[7]_PORT_B_address_reg = DFFE(D1_q_a[7]_PORT_B_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_PORT_A_write_enable = WR;
D1_q_a[7]_PORT_A_write_enable_reg = DFFE(D1_q_a[7]_PORT_A_write_enable, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_clock_0 = CLOCK;
D1_q_a[7]_PORT_A_data_out = MEMORY(D1_q_a[7]_PORT_A_data_in_reg, , D1_q_a[7]_PORT_A_address_reg, D1_q_a[7]_PORT_B_address_reg, D1_q_a[7]_PORT_A_write_enable_reg, , , , D1_q_a[7]_clock_0, , , , , );
D1_q_a[7] = D1_q_a[7]_PORT_A_data_out[0];


--WR is WR
--operation mode is input

WR = INPUT();


--CLOCK is CLOCK
--operation mode is input

CLOCK = INPUT();


--DATAIN[0] is DATAIN[0]
--operation mode is input

DATAIN[0] = INPUT();


--ADDR[0] is ADDR[0]
--operation mode is input

ADDR[0] = INPUT();


--ADDR[1] is ADDR[1]
--operation mode is input

ADDR[1] = INPUT();


--ADDR[2] is ADDR[2]
--operation mode is input

ADDR[2] = INPUT();


--ADDR[3] is ADDR[3]
--operation mode is input

ADDR[3] = INPUT();


--ADDR[4] is ADDR[4]
--operation mode is input

ADDR[4] = INPUT();


--DATAIN[1] is DATAIN[1]
--operation mode is input

DATAIN[1] = INPUT();


--DATAIN[2] is DATAIN[2]
--operation mode is input

DATAIN[2] = INPUT();


--DATAIN[3] is DATAIN[3]
--operation mode is input

DATAIN[3] = INPUT();


--DATAIN[4] is DATAIN[4]
--operation mode is input

DATAIN[4] = INPUT();


--DATAIN[5] is DATAIN[5]
--operation mode is input

DATAIN[5] = INPUT();


--DATAIN[6] is DATAIN[6]
--operation mode is input

DATAIN[6] = INPUT();


--DATAIN[7] is DATAIN[7]
--operation mode is input

DATAIN[7] = INPUT();


--DATAOUT[0] is DATAOUT[0]
--operation mode is output

DATAOUT[0] = OUTPUT(D1_q_a[0]);


--DATAOUT[1] is DATAOUT[1]
--operation mode is output

DATAOUT[1] = OUTPUT(D1_q_a[1]);


--DATAOUT[2] is DATAOUT[2]
--operation mode is output

DATAOUT[2] = OUTPUT(D1_q_a[2]);


--DATAOUT[3] is DATAOUT[3]
--operation mode is output

DATAOUT[3] = OUTPUT(D1_q_a[3]);


--DATAOUT[4] is DATAOUT[4]
--operation mode is output

DATAOUT[4] = OUTPUT(D1_q_a[4]);


--DATAOUT[5] is DATAOUT[5]
--operation mode is output

DATAOUT[5] = OUTPUT(D1_q_a[5]);


--DATAOUT[6] is DATAOUT[6]
--operation mode is output

DATAOUT[6] = OUTPUT(D1_q_a[6]);


--DATAOUT[7] is DATAOUT[7]
--operation mode is output

DATAOUT[7] = OUTPUT(D1_q_a[7]);