代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/290020/8511827
c 数字示波器.c
// Header: 数字示波器
// File Name:lcdII.c
// Author: H.C.H
// Date:2005/8/15
//说明：基本成功
#include
#include
#include
#define uint unsigned int
#define uchar unsi
www.eeworm.com/read/374543/9396985
hier_info tri_s11.hier_info
|tri_s11
enaddr2 => oaddr365[10]~10.OE
enaddr2 => oaddr365[9]~9.OE
enaddr2 => oaddr365[8]~8.OE
enaddr2 => oaddr365[7]~7.OE
enaddr2 => oaddr365[6]~6.OE
enaddr2 => oaddr365[5]~5.OE
enaddr2 => oad
www.eeworm.com/read/366116/9832284
hier_info rcvr.hier_info
|uart
sdo txt:inst1.clk
clk => rcvr:inst.clk
wrn => txt:inst1.wrn
din[0] => txt:inst1.din[0]
din[1] => txt:inst1.din[1]
din[2] => txt:inst1.din[2]
din[3] => txt:inst1.d
www.eeworm.com/read/364280/9914466
v dac_test.v
/* DAC_TLC5620测试模块
* 按KEY1键，通道D的电压值递增;
* 按KEY2键，通道C的电压值递增;
* 按KEY3键，通道B的电压值递增;
* 按KEY4键，通道A的电压值递增;
* 各通道的电压值显示于数码管.
*/
module dac_test(clk,rst,key,wr_n,wr_data,seg_com,seg_data);
input
www.eeworm.com/read/364280/9914520
bak dac_test.v.bak
module dac_test(clk,rst,key,wr_n,wr_data,seg_com,seg_data);
input clk;
input rst;
input[3:0] key;
output wr_n;
output [10:0] wr_data;
output [7:0]seg_data;
output [7
www.eeworm.com/read/363302/9960574
hier_info openlock.hier_info
|openlock
clk => lockclose~reg0.CLK
clk => lockopen~reg0.CLK
clk => temp5[0].CLK
clk => temp5[1].CLK
clk => temp5[2].CLK
clk => temp5[3].CLK
clk => temp4[0].CLK
clk => temp4[1].CLK
clk => tem
www.eeworm.com/read/160815/10497930
fir31_hier_info
|fir31
r => dff1:g1_29_dffx.r
r => dff1:g1_28_dffx.r
r => dff1:g1_27_dffx.r
r => dff1:g1_26_dffx.r
r => dff1:g1_25_dffx.r
r => dff1:g1_24_dffx.r
r => dff1:g1_23_dffx.r
r => dff1:g1_22_dffx.r
www.eeworm.com/read/350244/10755158
vhd vpc.vhd
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
www.eeworm.com/read/350244/10755206
vhd ad_control.vhd
library ieee;
use ieee.std_logic_1164.all;
entity ad_control is
port(busy:in std_logic;
datain:in std_logic_vector(7 downto 0);
clk:in std_logic;
dataout:out std_logic_vector(7 do
www.eeworm.com/read/275040/10838023
hier_info rcvr.hier_info
|uart
sdo txt:inst1.clk
clk => rcvr:inst.clk
wrn => txt:inst1.wrn
din[0] => txt:inst1.din[0]
din[1] => txt:inst1.din[1]
din[2] => txt:inst1.din[2]
din[3] => txt:inst1.d