vpc.vhd

电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY vpc IS 
	port
	(
		inclk :  IN  STD_LOGIC;
		busy :  IN  STD_LOGIC;
		datain :  IN  STD_LOGIC_VECTOR(7 downto 0);
		cs :  OUT  STD_LOGIC;
		rd :  OUT  STD_LOGIC;
		dataout1 :  OUT  STD_LOGIC_VECTOR(6 downto 0);
		dataout2 :  OUT  STD_LOGIC_VECTOR(6 downto 0);
		dataout3 :  OUT  STD_LOGIC_VECTOR(6 downto 0)
	);
END vpc;

ARCHITECTURE bdf_type OF vpc IS 

component ad_control
	PORT(busy : IN STD_LOGIC;
		 clk : IN STD_LOGIC;
		 datain : IN STD_LOGIC_VECTOR(7 downto 0);
		 cs : OUT STD_LOGIC;
		 rd : OUT STD_LOGIC;
		 dataout : OUT STD_LOGIC_VECTOR(7 downto 0)
	);
end component;

component code
	PORT(datain : IN STD_LOGIC_VECTOR(7 downto 0);
		 dataout1 : OUT STD_LOGIC_VECTOR(6 downto 0);
		 dataout2 : OUT STD_LOGIC_VECTOR(6 downto 0);
		 dataout3 : OUT STD_LOGIC_VECTOR(6 downto 0)
	);
end component;

component division
	PORT(clk : IN STD_LOGIC;
		 outclk : OUT STD_LOGIC
	);
end component;

signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(7 downto 0);


BEGIN 



b2v_inst : ad_control
PORT MAP(busy => busy,
		 clk => SYNTHESIZED_WIRE_0,
		 datain => datain,
		 cs => cs,
		 rd => rd,
		 dataout => SYNTHESIZED_WIRE_1);

b2v_inst1 : code
PORT MAP(datain => SYNTHESIZED_WIRE_1,
		 dataout1 => dataout1,
		 dataout2 => dataout2,
		 dataout3 => dataout3);

b2v_inst2 : division
PORT MAP(clk => inclk,
		 outclk => SYNTHESIZED_WIRE_0);

END;