ad_control.vhd

来自「电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
entity ad_control is
port(busy:in std_logic;
     datain:in std_logic_vector(7 downto 0);
     clk:in std_logic;
     dataout:out std_logic_vector(7 downto 0);
     cs:out std_logic;
     rd:out std_logic);
end ad_control;
architecture behav of ad_control is
 type state_type is(s0,s1,s2,s3,s4);
 signal state:state_type;
 begin
 process(clk)
 begin
  if clk'event and clk='1' then
    case state is
       when s0=>
         state<=s2;
       when s1=>
         state<=s2;
         cs<='1';
         rd<='1';
         dataout<=datain;
       when s2=>
         cs<='0';
         rd<='0';
         state<=s3;
       when s3=>
         state<=s4;
       when s4=>
         if busy='0' then
           state<=s3;
         else state<=s1;
         end if;
       when others=>
           state<=s0; 
       end case; 
    end if;
 end process;
 end behav;