代码搜索：dataIn

找到约 2,888 项符合「dataIn」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/206514/15294006

v iq_pn_gen.v

/* The following is example code that implements two LFSRs which can be used as part of pn generators. The number of taps are fixed however the tap points and LFSR width are parameratized. This code
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www.eeworm.com/read/206514/15294026

v iq_pn_gen.v

/* The following is example code that implements two LFSRs which can be used as part of pn generators. The number of taps are fixed however the tap points and LFSR width are parameratized. This cod
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www.eeworm.com/read/474310/6819665

hier_info tlc5510.hier_info

|tlc5510 RST => STA_G_CURRENTSTATE.ACLR RST => DATA[7]~reg0.ACLR RST => DATA[6]~reg0.ACLR RST => DATA[5]~reg0.ACLR RST => DATA[4]~reg0.ACLR RST => DATA[3]~reg0.ACLR RST => DATA[2]~reg0.ACLR RS
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www.eeworm.com/read/392763/8327799

hier_info compare.hier_info

|compare ok => f0[1].LATCH_ENABLE ok => f0[2].LATCH_ENABLE ok => f0[3].LATCH_ENABLE ok => f0[4].LATCH_ENABLE ok => f0[5].LATCH_ENABLE ok => f0[0].LATCH_ENABLE clk => g0.CLK d[0] => Equal0.IN5
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bak segmain.v.bak

module segmain(clk,reset_n,datain,seg_data,seg_com); input clk; input reset_n; input [15:0] datain; output [7:0]seg_data; output [3:0]seg_com; reg [3:0]seg_com; reg [7:0]seg_data; reg [3:0
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www.eeworm.com/read/370136/9615891

v segmain.v

module segmain(clk,reset_n,datain,seg_data,seg_com); input clk; input reset_n; input [15:0] datain; output [7:0]seg_data; output [3:0]seg_com; reg [3:0]seg_com; reg [7:0]seg_data; reg [3:0
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www.eeworm.com/read/412209/11211049

hier_info ch8_matrix.hier_info

|CH8_Matrix PS10 my_DFF:inst10.D PC0 => led1.DATAIN CLK_40M => div_mult:inst8.clk flagb => gating_pulse:inst.FlagB flagb => inst6.IN0 TB_DDS
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www.eeworm.com/read/236691/14002147

hier_info hdb3decoder.hier_info

|HDB3DECODER POS_IN => POS_IN_TMP.DATAIN NEG_IN => NEG_IN_TMP.DATAIN CLK => NEG_IN_TMP.CLK CLK => NRZ~reg0.CLK CLK => POS_IN_TMP.CLK CLK => SEQUENCE[2].CLK CLK => SEQUENCE[1].CLK CLK => SEQUEN
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www.eeworm.com/read/200691/15427515

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity leg is port( d_irq : in vl_logic_vector(1 downto 0); d_re : out vl_logic; d_we : ou
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www.eeworm.com/read/17578/739737

m rrcsend.m

function dataout=RRCsend(datain,Fs,nsamp,delay); num =rcosine(Fs,Fs*nsamp,'fir/sqrt',0.22,delay); %滤波器抽头系数 dataoutr=rcosflt(real(datain),Fs,Fs*nsamp,'filter',num); dataouti=rcosflt(imag(datain),Fs
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