_primary.vhd

verilog hdl编写,六段流水线CPU.程序完整

library verilog;
use verilog.vl_types.all;
entity leg is
    port(
        d_irq           : in     vl_logic_vector(1 downto 0);
        d_re            : out    vl_logic;
        d_we            : out    vl_logic;
        d_addr          : out    vl_logic_vector(31 downto 0);
        d_datain        : in     vl_logic_vector(31 downto 0);
        d_dataout       : out    vl_logic_vector(31 downto 0);
        d_wait          : in     vl_logic;
        d_be            : out    vl_logic_vector(3 downto 0);
        i_datain        : in     vl_logic_vector(31 downto 0);
        i_addr          : out    vl_logic_vector(31 downto 0);
        i_read          : out    vl_logic;
        i_wait          : in     vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic
    );
end leg;