代码搜索:dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
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vhd tb.vhd

library ieee; use ieee.std_logic_1164.all; entity tb is end tb; architecture arch of tb is component shift_reg port( datain : in std_logic; clk : in std_logic; rst : in std_logi
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hier_info enll.hier_info

|ENLL ln[32]
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hier_info rr.hier_info

|RR rr[0]
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vhd moore1.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MOORE1 IS PORT (DATAIN :IN STD_LOGIC_VECTOR(1 DOWNTO 0); CLK,RST : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO
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txt crc32-digit.txt

100000100110000010001110110110111= 104C11DB7 datain=1111010100000100001110111001100100000000000000000000000000000000
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vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity io_buf_opdrn is port( datain : in vl_logic; dataout : out vl_logic ); end io_buf_opdrn;
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hier_info fifo.hier_info

|fifo clk => ram_22.CLK clk => ram_23.CLK clk => ram_24.CLK clk => ram_25.CLK clk => ram_26.CLK clk => ram_27.CLK clk => ram_28.CLK clk => ram_29.CLK clk => ram_30.CLK clk => ram_31.CLK clk
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rpt da_tlc5620.tan.rpt

Classic Timing Analyzer report for DA_TLC5620 Tue Jan 15 13:02:38 2008 Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version --------------------- ; Table of Contents ; -
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vhd segmain.vhd

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity segmain is PORT( clk : IN STD_LOGIC; rst : IN STD_LOGIC; datain : IN STD_LOGIC_VECTOR(15 DO
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bak segmain.vhd.bak

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity segmain is PORT( clk : IN STD_LOGIC; rst : IN STD_LOGIC; datain : IN STD_LOGIC_VECTOR(15 DO