代码搜索：dataIn

找到约 2,888 项符合「dataIn」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/325485/13201394

asm bf533_omnivision_config.asm

/******************************************************************************/ // // Name: BF533 EZ-KIT video ITU-656 receive mode (8bit) for the Omnivision chip OV6630 // /*********************
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www.eeworm.com/read/137912/13279968

vhd fpga_s51_0.vhd

library ieee; use ieee.std_logic_1164.all; entity FPGA_S51_0 is port( p0:inout std_logic_vector(7 downto 0); --p2:in std_logic_vector(7 downto 0); wr,rd:in std_logic;
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www.eeworm.com/read/323539/13337020

c logic.c

#include #include //#include //#include #include "logic.h" #define DATAIN PINA #define DATADIR DDRA #define DATAOUT PORTA #defi
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www.eeworm.com/read/321790/13398962

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity io_buf_tri is port( datain : in vl_logic; dataout : out vl_logic; oe : in vl_logi
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www.eeworm.com/read/320930/13415815

v md5_padding.v

/******************************************************************************** * Module : md5_padding * Description: md5 Padding block * ****************************************************
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www.eeworm.com/read/320069/13433526

rpt part1.sim.rpt

Simulator report for part1 Thu Apr 10 21:35:01 2008 Version 6.0 Build 178 04/27/2006 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2.
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www.eeworm.com/read/319928/13439431

hier_info alu.hier_info

|ALU reset => reg:B_reg.clr reset => reg:A_reg.clr reset => C~0.OUTPUTSELECT reset => Z~0.OUTPUTSELECT clk => reg:B_reg.clock clk => reg:A_reg.clock OP[0] => Mux~0.IN5 OP[0] => Mux~1.IN6 OP[0
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www.eeworm.com/read/315109/13551988

hier_info alu.hier_info

|alu reset => result_t[15].ACLR reset => result_t[14].ACLR reset => result_t[13].ACLR reset => result_t[12].ACLR reset => result_t[11].ACLR reset => result_t[10].ACLR reset => result_t[9].ACLR
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www.eeworm.com/read/308751/13693612

ant arm.ant

// E:\ISE6.1\TST // Verilog Annotation Test Bench created by // HDL Bencher 6.1i // Sun May 06 09:28:57 2007 `timescale 1ns/1ns `define F_ASSERT 2 `define s3 3 `define N 5 `define IF1 2 `
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www.eeworm.com/read/308751/13693619

ant armtst_tbw.ant

// E:\ISE6.1\TST // Verilog Annotation Test Bench created by // HDL Bencher 6.1i // Fri Apr 27 09:33:14 2007 `timescale 1ns/1ns `define C_WRITE 4 `define C_L_MODE 0 `define C_P_CHRG 2 `def
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