alu.hier_info

ALU可以实现16种操作（包括加减乘除移位运算等）

|ALU
reset => reg:B_reg.clr
reset => reg:A_reg.clr
reset => C~0.OUTPUTSELECT
reset => Z~0.OUTPUTSELECT
clk => reg:B_reg.clock
clk => reg:A_reg.clock
OP[0] => Mux~0.IN5
OP[0] => Mux~1.IN6
OP[0] => Mux~2.IN5
OP[0] => Mux~3.IN5
OP[0] => Mux~4.IN5
OP[0] => Mux~5.IN5
OP[0] => Mux~6.IN5
OP[0] => Mux~7.IN5
OP[0] => Mux~8.IN5
OP[0] => Mux~9.IN5
OP[0] => Mux~10.IN5
OP[0] => Mux~11.IN5
OP[0] => Mux~12.IN5
OP[0] => Mux~13.IN5
OP[0] => Mux~14.IN5
OP[0] => Mux~15.IN6
OP[0] => Mux~16.IN11
OP[0] => Mux~17.IN19
OP[1] => Mux~0.IN4
OP[1] => Mux~1.IN5
OP[1] => Mux~2.IN4
OP[1] => Mux~3.IN4
OP[1] => Mux~4.IN4
OP[1] => Mux~5.IN4
OP[1] => Mux~6.IN4
OP[1] => Mux~7.IN4
OP[1] => Mux~8.IN4
OP[1] => Mux~9.IN4
OP[1] => Mux~10.IN4
OP[1] => Mux~11.IN4
OP[1] => Mux~12.IN4
OP[1] => Mux~13.IN4
OP[1] => Mux~14.IN4
OP[1] => Mux~15.IN5
OP[1] => Mux~16.IN10
OP[1] => Mux~17.IN18
OP[2] => Mux~0.IN3
OP[2] => Mux~1.IN4
OP[2] => Mux~2.IN3
OP[2] => Mux~3.IN3
OP[2] => Mux~4.IN3
OP[2] => Mux~5.IN3
OP[2] => Mux~6.IN3
OP[2] => Mux~7.IN3
OP[2] => Mux~8.IN3
OP[2] => Mux~9.IN3
OP[2] => Mux~10.IN3
OP[2] => Mux~11.IN3
OP[2] => Mux~12.IN3
OP[2] => Mux~13.IN3
OP[2] => Mux~14.IN3
OP[2] => Mux~15.IN4
OP[2] => Mux~16.IN9
OP[2] => Mux~17.IN17
OP[3] => Mux~0.IN2
OP[3] => Mux~1.IN3
OP[3] => Mux~2.IN2
OP[3] => Mux~3.IN2
OP[3] => Mux~4.IN2
OP[3] => Mux~5.IN2
OP[3] => Mux~6.IN2
OP[3] => Mux~7.IN2
OP[3] => Mux~8.IN2
OP[3] => Mux~9.IN2
OP[3] => Mux~10.IN2
OP[3] => Mux~11.IN2
OP[3] => Mux~12.IN2
OP[3] => Mux~13.IN2
OP[3] => Mux~14.IN2
OP[3] => Mux~15.IN3
OP[3] => Mux~16.IN8
OP[3] => Mux~17.IN16
sel => reg:B_reg.sel
sel => reg:A_reg.sel
write => reg:B_reg.write
write => reg:A_reg.write
Dinput[0] => reg:B_reg.D[0]
Dinput[0] => reg:A_reg.D[0]
Dinput[1] => reg:B_reg.D[1]
Dinput[1] => reg:A_reg.D[1]
Dinput[2] => reg:B_reg.D[2]
Dinput[2] => reg:A_reg.D[2]
Dinput[3] => reg:B_reg.D[3]
Dinput[3] => reg:A_reg.D[3]
Dinput[4] => reg:B_reg.D[4]
Dinput[4] => reg:A_reg.D[4]
Dinput[5] => reg:B_reg.D[5]
Dinput[5] => reg:A_reg.D[5]
Dinput[6] => reg:B_reg.D[6]
Dinput[6] => reg:A_reg.D[6]
Dinput[7] => reg:B_reg.D[7]
Dinput[7] => reg:A_reg.D[7]
Dinput[8] => reg:B_reg.D[8]
Dinput[8] => reg:A_reg.D[8]
Dinput[9] => reg:B_reg.D[9]
Dinput[9] => reg:A_reg.D[9]
Dinput[10] => reg:B_reg.D[10]
Dinput[10] => reg:A_reg.D[10]
Dinput[11] => reg:B_reg.D[11]
Dinput[11] => reg:A_reg.D[11]
Dinput[12] => reg:B_reg.D[12]
Dinput[12] => reg:A_reg.D[12]
Dinput[13] => reg:B_reg.D[13]
Dinput[13] => reg:A_reg.D[13]
Dinput[14] => reg:B_reg.D[14]
Dinput[14] => reg:A_reg.D[14]
Dinput[15] => reg:B_reg.D[15]
Dinput[15] => reg:A_reg.D[15]
cin => add~3.IN17
cin => add~5.IN34
result[0] <= Mux~15.DB_MAX_OUTPUT_PORT_TYPE
result[1] <= Mux~14.DB_MAX_OUTPUT_PORT_TYPE
result[2] <= Mux~13.DB_MAX_OUTPUT_PORT_TYPE
result[3] <= Mux~12.DB_MAX_OUTPUT_PORT_TYPE
result[4] <= Mux~11.DB_MAX_OUTPUT_PORT_TYPE
result[5] <= Mux~10.DB_MAX_OUTPUT_PORT_TYPE
result[6] <= Mux~9.DB_MAX_OUTPUT_PORT_TYPE
result[7] <= Mux~8.DB_MAX_OUTPUT_PORT_TYPE
result[8] <= Mux~7.DB_MAX_OUTPUT_PORT_TYPE
result[9] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
result[10] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
result[11] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
result[12] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
result[13] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
result[14] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
result[15] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
C <= C~0.DB_MAX_OUTPUT_PORT_TYPE
Z <= Z~0.DB_MAX_OUTPUT_PORT_TYPE


|ALU|reg:A_reg
clr => Q[14]~reg0.ACLR
clr => Q[13]~reg0.ACLR
clr => Q[12]~reg0.ACLR
clr => Q[11]~reg0.ACLR
clr => Q[10]~reg0.ACLR
clr => Q[9]~reg0.ACLR
clr => Q[8]~reg0.ACLR
clr => Q[7]~reg0.ACLR
clr => Q[6]~reg0.ACLR
clr => Q[5]~reg0.ACLR
clr => Q[4]~reg0.ACLR
clr => Q[3]~reg0.ACLR
clr => Q[2]~reg0.ACLR
clr => Q[1]~reg0.ACLR
clr => Q[0]~reg0.ACLR
clr => Q[15]~reg0.ACLR
D[0] => Q[0]~reg0.DATAIN
D[1] => Q[1]~reg0.DATAIN
D[2] => Q[2]~reg0.DATAIN
D[3] => Q[3]~reg0.DATAIN
D[4] => Q[4]~reg0.DATAIN
D[5] => Q[5]~reg0.DATAIN
D[6] => Q[6]~reg0.DATAIN
D[7] => Q[7]~reg0.DATAIN
D[8] => Q[8]~reg0.DATAIN
D[9] => Q[9]~reg0.DATAIN
D[10] => Q[10]~reg0.DATAIN
D[11] => Q[11]~reg0.DATAIN
D[12] => Q[12]~reg0.DATAIN
D[13] => Q[13]~reg0.DATAIN
D[14] => Q[14]~reg0.DATAIN
D[15] => Q[15]~reg0.DATAIN
clock => Q[14]~reg0.CLK
clock => Q[13]~reg0.CLK
clock => Q[12]~reg0.CLK
clock => Q[11]~reg0.CLK
clock => Q[10]~reg0.CLK
clock => Q[9]~reg0.CLK
clock => Q[8]~reg0.CLK
clock => Q[7]~reg0.CLK
clock => Q[6]~reg0.CLK
clock => Q[5]~reg0.CLK
clock => Q[4]~reg0.CLK
clock => Q[3]~reg0.CLK
clock => Q[2]~reg0.CLK
clock => Q[1]~reg0.CLK
clock => Q[0]~reg0.CLK
clock => Q[15]~reg0.CLK
write => process0~0.IN0
sel => process0~0.IN1
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[10] <= Q[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[11] <= Q[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[12] <= Q[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[13] <= Q[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[14] <= Q[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[15] <= Q[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ALU|reg:B_reg
clr => Q[14]~reg0.ACLR
clr => Q[13]~reg0.ACLR
clr => Q[12]~reg0.ACLR
clr => Q[11]~reg0.ACLR
clr => Q[10]~reg0.ACLR
clr => Q[9]~reg0.ACLR
clr => Q[8]~reg0.ACLR
clr => Q[7]~reg0.ACLR
clr => Q[6]~reg0.ACLR
clr => Q[5]~reg0.ACLR
clr => Q[4]~reg0.ACLR
clr => Q[3]~reg0.ACLR
clr => Q[2]~reg0.ACLR
clr => Q[1]~reg0.ACLR
clr => Q[0]~reg0.ACLR
clr => Q[15]~reg0.ACLR
D[0] => Q[0]~reg0.DATAIN
D[1] => Q[1]~reg0.DATAIN
D[2] => Q[2]~reg0.DATAIN
D[3] => Q[3]~reg0.DATAIN
D[4] => Q[4]~reg0.DATAIN
D[5] => Q[5]~reg0.DATAIN
D[6] => Q[6]~reg0.DATAIN
D[7] => Q[7]~reg0.DATAIN
D[8] => Q[8]~reg0.DATAIN
D[9] => Q[9]~reg0.DATAIN
D[10] => Q[10]~reg0.DATAIN
D[11] => Q[11]~reg0.DATAIN
D[12] => Q[12]~reg0.DATAIN
D[13] => Q[13]~reg0.DATAIN
D[14] => Q[14]~reg0.DATAIN
D[15] => Q[15]~reg0.DATAIN
clock => Q[14]~reg0.CLK
clock => Q[13]~reg0.CLK
clock => Q[12]~reg0.CLK
clock => Q[11]~reg0.CLK
clock => Q[10]~reg0.CLK
clock => Q[9]~reg0.CLK
clock => Q[8]~reg0.CLK
clock => Q[7]~reg0.CLK
clock => Q[6]~reg0.CLK
clock => Q[5]~reg0.CLK
clock => Q[4]~reg0.CLK
clock => Q[3]~reg0.CLK
clock => Q[2]~reg0.CLK
clock => Q[1]~reg0.CLK
clock => Q[0]~reg0.CLK
clock => Q[15]~reg0.CLK
write => process0~0.IN0
sel => process0~0.IN1
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= Q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= Q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[10] <= Q[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[11] <= Q[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[12] <= Q[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[13] <= Q[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[14] <= Q[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[15] <= Q[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ALU|sub16:l2
A[0] => adder16:l1.a[0]
A[1] => adder16:l1.a[1]
A[2] => adder16:l1.a[2]
A[3] => adder16:l1.a[3]
A[4] => adder16:l1.a[4]
A[5] => adder16:l1.a[5]
A[6] => adder16:l1.a[6]
A[7] => adder16:l1.a[7]
A[8] => adder16:l1.a[8]
A[9] => adder16:l1.a[9]
A[10] => adder16:l1.a[10]
A[11] => adder16:l1.a[11]
A[12] => adder16:l1.a[12]
A[13] => adder16:l1.a[13]
A[14] => adder16:l1.a[14]
A[15] => adder16:l1.a[15]
B[0] => adder16:l1.b[0]
B[1] => adder16:l1.b[1]
B[2] => adder16:l1.b[2]
B[3] => adder16:l1.b[3]
B[4] => adder16:l1.b[4]
B[5] => adder16:l1.b[5]
B[6] => adder16:l1.b[6]
B[7] => adder16:l1.b[7]
B[8] => adder16:l1.b[8]
B[9] => adder16:l1.b[9]
B[10] => adder16:l1.b[10]
B[11] => adder16:l1.b[11]
B[12] => adder16:l1.b[12]
B[13] => adder16:l1.b[13]
B[14] => adder16:l1.b[14]
B[15] => adder16:l1.b[15]
cin => ~NO_FANOUT~
S_sum[0] <= adder16:l1.sum[0]
S_sum[1] <= adder16:l1.sum[1]
S_sum[2] <= adder16:l1.sum[2]
S_sum[3] <= adder16:l1.sum[3]
S_sum[4] <= adder16:l1.sum[4]
S_sum[5] <= adder16:l1.sum[5]
S_sum[6] <= adder16:l1.sum[6]
S_sum[7] <= adder16:l1.sum[7]
S_sum[8] <= adder16:l1.sum[8]
S_sum[9] <= adder16:l1.sum[9]
S_sum[10] <= adder16:l1.sum[10]
S_sum[11] <= adder16:l1.sum[11]
S_sum[12] <= adder16:l1.sum[12]
S_sum[13] <= adder16:l1.sum[13]
S_sum[14] <= adder16:l1.sum[14]
S_sum[15] <= adder16:l1.sum[15]
cout <= cout~0.DB_MAX_OUTPUT_PORT_TYPE


|ALU|sub16:l2|adder16:l1
a[0] => add4:u1.a[0]
a[1] => add4:u1.a[1]
a[2] => add4:u1.a[2]
a[3] => add4:u1.a[3]
a[4] => add4:u2.a[0]
a[5] => add4:u2.a[1]
a[6] => add4:u2.a[2]
a[7] => add4:u2.a[3]
a[8] => add4:u3.a[0]
a[9] => add4:u3.a[1]
a[10] => add4:u3.a[2]
a[11] => add4:u3.a[3]
a[12] => add4:u4.a[0]
a[13] => add4:u4.a[1]
a[14] => add4:u4.a[2]
a[15] => add4:u4.a[3]
b[0] => add4:u1.b[0]
b[1] => add4:u1.b[1]
b[2] => add4:u1.b[2]
b[3] => add4:u1.b[3]
b[4] => add4:u2.b[0]
b[5] => add4:u2.b[1]
b[6] => add4:u2.b[2]
b[7] => add4:u2.b[3]
b[8] => add4:u3.b[0]
b[9] => add4:u3.b[1]
b[10] => add4:u3.b[2]
b[11] => add4:u3.b[3]
b[12] => add4:u4.b[0]
b[13] => add4:u4.b[1]
b[14] => add4:u4.b[2]
b[15] => add4:u4.b[3]
cin => c4~0.IN1
cin => c8~3.IN0
cin => c12~7.IN0
cin => cout~9.IN0
cin => add4:u1.cin
sum[0] <= add4:u1.sum[0]
sum[1] <= add4:u1.sum[1]
sum[2] <= add4:u1.sum[2]
sum[3] <= add4:u1.sum[3]