fpga_s51_0.vhd

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

library ieee;
use ieee.std_logic_1164.all;

entity FPGA_S51_0 is
port(
  p0:inout std_logic_vector(7 downto 0);      
  --p2:in std_logic_vector(7 downto 0);          
  wr,rd:in std_logic;               
  ale:in std_logic;			        
  --input_cs:in std_logic;		       
  datain1:in std_logic_vector(7 downto  0); 
  datain2:in std_logic_vector(7 downto  0);
  datain3:in std_logic_vector(7 downto  0);
  datain4:in std_logic_vector(7 downto  0);
  datain5:in std_logic_vector(7 downto  0);
  datain6:in std_logic_vector(7 downto  0);
  datain7:in std_logic_vector(7 downto  0);
  datain8:in std_logic_vector(7 downto  0); 	       
  dataout1:out std_logic_vector(7 downto 0);
  dataout2:out std_logic_vector(7 downto 0);
  dataout3:out std_logic_vector(7 downto 0);
  dataout4:out std_logic_vector(7 downto 0));   
               
end FPGA_S51_0;

architecture behav of FPGA_S51_0 is
 signal latch_address:std_logic_vector(7 downto 0);
 --signal latch_out1:std_logic_vector(7 downto 0);
 --signal latch_out2:std_logic_vector(7 downto 0);
 --signal latch_in1:std_logic_vector(7 downto 0);
 --signal latch_in2:std_logic_vector(7 downto 0);
 --signal wr_enable1:std_logic;
 --signal wr_enable2:std_logic;
 
begin	
 process(ale)    
 begin
   if  ale'event and  ale='0' then
      latch_address<=p0;    
   end if;
 end process;

 process(latch_address,wr)    
 begin
    if wr'event and wr='1'then
        case latch_address is
          when"00000000"=>dataout1<=p0;
          when"00000001"=>dataout2<=p0;
          when"00000010"=>dataout3<=p0;
          when"00000011"=>dataout4<=p0;
          when others=>null;
        end case;
   end if;
end process;

process(latch_address,rd)
  begin
   if rd'event and rd='1'then
       case latch_address is
          when"00000100"=>p0<=datain1;
          when"00000101"=>p0<=datain2;
          when"00000110"=>p0<=datain3;
          when"00000111"=>p0<=datain4;
          when"00001000"=>p0<=datain5;
          when"00001001"=>p0<=datain6;
          when"00001010"=>p0<=datain7;
          when"00001011"=>p0<=datain8;
          when others=>p0<="ZZZZZZZZ";
        end case;
     end if;
end process;
  
  end behav;