代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/284052/8968877
c picusbnut.c
#include
#fuses HSPLL,USBDIV,PLL5,CPUDIV1,VREGEN,NOWDT,NOPROTECT,NOLVP,NODEBUG
#use delay(clock=48000000)
/////////////////////////////////////////////////////////////////////////////
www.eeworm.com/read/426736/9002566
vhd testda.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity testda is
port(clk:in std_logic;
data:out std_logic_vector(7 downto 0);
www.eeworm.com/read/382033/9057182
hier_info division_a.hier_info
|division_A
pa => pareg~reg0.DATAIN
pa => always0~1.IN1
pb => Decoder0.IN0
pb => pbreg~reg0.DATAIN
pb => always0~0.IN1
clk => pareg~reg0.CLK
clk => pbreg~reg0.CLK
clk => beginning~reg0.CLK
db
www.eeworm.com/read/381044/9113182
vhd testda.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity testda is
port(clk:in std_logic;
data:out std_logic_vector(7 downto 0);
www.eeworm.com/read/377612/9269624
th ramtestbench.th
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dualram_tb is
end entity;
architecture Behavioral of dualram_tb is
constant
www.eeworm.com/read/374530/9399662
vhd testda.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity testda is
port(clk:in std_logic;
data:out std_logic_vector(7 downto 0);
www.eeworm.com/read/177619/9443916
vhd bingzhuanchuan.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity bingzhuanchuan is
Port (cp:in std_logic;
cs:in std_logic;
datain:in s
www.eeworm.com/read/177025/9474157
c convolution_encoder.c
/*****************************************************************************/
/* FIle Name : convolution_encoder.c */
/* Description : WLAN FEC convolution_
www.eeworm.com/read/176923/9479462
vhd dataget.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dataget IS
PORT(datain:IN STD_LOGIC_VECTOR(23 DOWNTO 0);
clk_dsp:IN STD_LOGIC