dataget.vhd

来自「用max+plusII编写的vhdl程序 乒乓球游戏机」· VHDL 代码 · 共 46 行

LIBRARY	IEEE;
USE	IEEE.STD_LOGIC_1164.ALL;
USE	IEEE.STD_LOGIC_ARITH.ALL;
USE	IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY dataget IS
PORT(datain:IN	STD_LOGIC_VECTOR(23 DOWNTO 0);
	clk_dsp:IN  STD_LOGIC;
	scan:	OUT	STD_LOGIC_VECTOR(5	DOWNTO	0);
	bcdout: OUT	STD_LOGIC_VECTOR(0 TO 3)
	);
END dataget;

ARCHITECTURE behave OF dataget IS
SIGNAL	S:	STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
BEGIN
U1:PROCESS(clk_dsp)
BEGIN
IF(clk_dsp'EVENT AND clk_dsp='1')THEN
IF(S<=4)THEN
S<=S+1;
ELSE
S<="000";
END IF;
END IF;
END PROCESS U1;

U2:PROCESS(s,datain)
BEGIN
CASE s IS
WHEN	"000"=>	bcdout<=datain(3 downto 0);
				scan<="100000";
when	"001"=> bcdout<=datain(7 downto 4);
				scan<="010000";
when	"010"=>	bcdout<=datain(11 downto 8);
				scan<="001000";
when	"011"=> bcdout<=datain(15 downto 12);
				scan<="000100";
when	"100"=>	bcdout<=datain(19 downto 16);
				scan<="000010";
when	others=> bcdout<=datain(23 downto 20);
				scan<="000001";
END	CASE;
END PROCESS U2;
END behave;