代码搜索:dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
www.eeworm.com/read/103953/6582252

edf data_input.edf

(edif (rename data_input "input_data") (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2004 4 25 11 0 26) (author "Synplicity
www.eeworm.com/read/204953/15330926

vhd crc8.vhd

library ieee; use ieee.std_logic_1164.all; entity crc8 is port( clk:in std_logic; rst:in std_logic; datain: in std_logic; rstout:out std_logic; dataout: out std_l
www.eeworm.com/read/426991/8987751

hier_info ram.hier_info

|ram addr[0] => data1.RADDR addr[0] => data1.WADDR addr[1] => data1.RADDR1 addr[1] => data1.WADDR1 addr[2] => data1.RADDR2 addr[2] => data1.WADDR2 addr[3] => data1.RADDR3 addr[3] => data1.WADD
www.eeworm.com/read/386805/8726572

v data_in_reg.v

/********************************************************* MODULE: Sub Level SDRAM Controller Data input register FILE NAME: data_in_reg.v VERSION: 1.0 DATE: April 28th, 2002 AUTHOR: Ho
www.eeworm.com/read/422910/10603491

v data_in_reg.v

/********************************************************* MODULE: Sub Level SDRAM Controller Data input register FILE NAME: data_in_reg.v VERSION: 1.0 DATE: April 28th, 2002 AUTHOR: Hossein
www.eeworm.com/read/467788/7001451

hier_info fifo2.hier_info

|fifo2 clk => dout[14]~reg0.CLK clk => dout[13]~reg0.CLK clk => dout[12]~reg0.CLK clk => dout[11]~reg0.CLK clk => dout[10]~reg0.CLK clk => dout[9]~reg0.CLK clk => dout[8]~reg0.CLK clk => dout[
www.eeworm.com/read/141583/12996879

v data_in_reg.v

/********************************************************* MODULE: Sub Level SDRAM Controller Data input register FILE NAME: data_in_reg.v VERSION: 1.0 DATE: April 28th, 2002 AUTHOR: Ho
www.eeworm.com/read/139313/13163554

hier_info lightw.hier_info

|lightW testout0 div:inst.clk testout1
www.eeworm.com/read/320897/13416769

rpt pcpu.fit.rpt

Fitter report for pcpu Tue Jan 15 16:07:55 2008 Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version --------------------- ; Table of Contents ; ---------------------
www.eeworm.com/read/419416/10868901

spl data_part.spl

[Inputs] =datain[11:0]= [Outputs] =dataout1[1:0]= =dataout2[1:0]= =dataout3[1:0]= =dataout4[1:0]= =dataout5[1:0]= =dataout6[1:0]= [BiDir]